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# configuration file for util/mkerr.pl

# The INPUT HEADER is scanned for declarations
# LIBNAME       INPUT HEADER                    ERROR-TABLE FILE
L ERR           NONE                            NONE
L BN            include/openssl/bn.h            crypto/bn/bn_err.c
L RSA           include/openssl/rsa.h           crypto/rsa/rsa_err.c
L DH            include/openssl/dh.h            crypto/dh/dh_err.c
L EVP           include/openssl/evp.h           crypto/evp/evp_err.c
L BUF           include/openssl/buffer.h        crypto/buffer/buf_err.c
L OBJ           include/openssl/objects.h       crypto/objects/obj_err.c
L PEM           include/openssl/pem.h           crypto/pem/pem_err.c
L DSA           include/openssl/dsa.h           crypto/dsa/dsa_err.c
L X509          include/openssl/x509.h          crypto/x509/x509_err.c
L ASN1          include/openssl/asn1.h          crypto/asn1/asn1_err.c
L CONF          include/openssl/conf.h          crypto/conf/conf_err.c
L CRYPTO        include/openssl/crypto.h        crypto/cpt_err.c
L EC            include/openssl/ec.h            crypto/ec/ec_err.c
L SSL           include/openssl/ssl.h           ssl/ssl_err.c
L BIO           include/openssl/bio.h           crypto/bio/bio_err.c
L PKCS7         include/openssl/pkcs7.h         crypto/pkcs7/pkcs7err.c
L X509V3        include/openssl/x509v3.h        crypto/x509v3/v3err.c
L PKCS12        include/openssl/pkcs12.h        crypto/pkcs12/pk12err.c
L RAND          include/openssl/rand.h          crypto/rand/rand_err.c
L DSO           include/internal/dso.h          crypto/dso/dso_err.c
L ENGINE        include/openssl/engine.h        crypto/engine/eng_err.c
L OCSP          include/openssl/ocsp.h          crypto/ocsp/ocsp_err.c
L UI            include/openssl/ui.h            crypto/ui/ui_err.c
L COMP          include/openssl/comp.h          crypto/comp/comp_err.c
L TS            include/openssl/ts.h            crypto/ts/ts_err.c
L CMS           include/openssl/cms.h           crypto/cms/cms_err.c
L CT            include/openssl/ct.h            crypto/ct/ct_err.c
L ASYNC         include/openssl/async.h         crypto/async/async_err.c
L KDF           include/openssl/kdf.h           crypto/kdf/kdf_err.c
L SM2           crypto/include/internal/sm2.h   crypto/sm2/sm2_err.c
L OSSL_STORE    include/openssl/store.h         crypto/store/store_err.c
L ESS           include/openssl/ess.h           crypto/ess/ess_err.c
L PROP          include/internal/property.h     crypto/property/property_err.c

# additional header files to be scanned for function names
L NONE          include/openssl/x509_vfy.h      NONE
L NONE          crypto/ec/ec_lcl.h              NONE
L NONE          crypto/cms/cms_lcl.h            NONE
L NONE          crypto/ct/ct_locl.h             NONE
L NONE          ssl/ssl_locl.h                  NONE

# SSL/TLS alerts
R SSL_R_SSLV3_ALERT_UNEXPECTED_MESSAGE          1010
R SSL_R_SSLV3_ALERT_BAD_RECORD_MAC              1020
R SSL_R_TLSV1_ALERT_DECRYPTION_FAILED           1021
R SSL_R_TLSV1_ALERT_RECORD_OVERFLOW             1022
R SSL_R_SSLV3_ALERT_DECOMPRESSION_FAILURE       1030
R SSL_R_SSLV3_ALERT_HANDSHAKE_FAILURE           1040
R SSL_R_SSLV3_ALERT_NO_CERTIFICATE              1041
R SSL_R_SSLV3_ALERT_BAD_CERTIFICATE             1042
R SSL_R_SSLV3_ALERT_UNSUPPORTED_CERTIFICATE     1043
R SSL_R_SSLV3_ALERT_CERTIFICATE_REVOKED         1044
R SSL_R_SSLV3_ALERT_CERTIFICATE_EXPIRED         1045
R SSL_R_SSLV3_ALERT_CERTIFICATE_UNKNOWN         1046
R SSL_R_SSLV3_ALERT_ILLEGAL_PARAMETER           1047
R SSL_R_TLSV1_ALERT_UNKNOWN_CA                  1048
R SSL_R_TLSV1_ALERT_ACCESS_DENIED               1049
R SSL_R_TLSV1_ALERT_DECODE_ERROR                1050
R SSL_R_TLSV1_ALERT_DECRYPT_ERROR               1051
R SSL_R_TLSV1_ALERT_EXPORT_RESTRICTION          1060
R SSL_R_TLSV1_ALERT_PROTOCOL_VERSION            1070
R SSL_R_TLSV1_ALERT_INSUFFICIENT_SECURITY       1071
R SSL_R_TLSV1_ALERT_INTERNAL_ERROR              1080
R SSL_R_TLSV1_ALERT_INAPPROPRIATE_FALLBACK      1086
R SSL_R_TLSV1_ALERT_USER_CANCELLED              1090
R SSL_R_TLSV1_ALERT_NO_RENEGOTIATION            1100
R SSL_R_TLSV13_ALERT_MISSING_EXTENSION          1109
R SSL_R_TLSV1_UNSUPPORTED_EXTENSION             1110
R SSL_R_TLSV1_CERTIFICATE_UNOBTAINABLE          1111
R SSL_R_TLSV1_UNRECOGNIZED_NAME                 1112
R SSL_R_TLSV1_BAD_CERTIFICATE_STATUS_RESPONSE   1113
R SSL_R_TLSV1_BAD_CERTIFICATE_HASH_VALUE        1114
R TLS1_AD_UNKNOWN_PSK_IDENTITY                  1115
R SSL_R_TLSV13_ALERT_CERTIFICATE_REQUIRED       1116
R TLS1_AD_NO_APPLICATION_PROTOCOL               1120
an class="p">, struct ata_device *adev) { pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); } /** * pdc202xx_configure_dmamode - set DMA mode in chip * @ap: ATA interface * @adev: ATA device * * Load DMA cycle times into the chip ready for a DMA transfer * to occur. */ static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; static u8 udma_timing[6][2] = { { 0x60, 0x03 }, /* 33 Mhz Clock */ { 0x40, 0x02 }, { 0x20, 0x01 }, { 0x40, 0x02 }, /* 66 Mhz Clock */ { 0x20, 0x01 }, { 0x20, 0x01 } }; static u8 mdma_timing[3][2] = { { 0xe0, 0x0f }, { 0x60, 0x04 }, { 0x60, 0x03 }, }; u8 r_bp, r_cp; pci_read_config_byte(pdev, port + 1, &r_bp); pci_read_config_byte(pdev, port + 2, &r_cp); r_bp &= ~0xE0; r_cp &= ~0x0F; if (adev->dma_mode >= XFER_UDMA_0) { int speed = adev->dma_mode - XFER_UDMA_0; r_bp |= udma_timing[speed][0]; r_cp |= udma_timing[speed][1]; } else { int speed = adev->dma_mode - XFER_MW_DMA_0; r_bp |= mdma_timing[speed][0]; r_cp |= mdma_timing[speed][1]; } pci_write_config_byte(pdev, port + 1, r_bp); pci_write_config_byte(pdev, port + 2, r_cp); } /** * pdc2026x_bmdma_start - DMA engine begin * @qc: ATA command * * In UDMA3 or higher we have to clock switch for the duration of the * DMA transfer sequence. * * Note: The host lock held by the libata layer protects * us from two channels both trying to set DMA bits at once */ static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct ata_device *adev = qc->dev; struct ata_taskfile *tf = &qc->tf; int sel66 = ap->port_no ? 0x08: 0x02; void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; void __iomem *clock = master + 0x11; void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); u32 len; /* Check we keep host level locking here */ if (adev->dma_mode > XFER_UDMA_2) iowrite8(ioread8(clock) | sel66, clock); else iowrite8(ioread8(clock) & ~sel66, clock); /* The DMA clocks may have been trashed by a reset. FIXME: make conditional and move to qc_issue ? */ pdc202xx_set_dmamode(ap, qc->dev); /* Cases the state machine will not complete correctly without help */ if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) { len = qc->nbytes / 2; if (tf->flags & ATA_TFLAG_WRITE) len |= 0x06000000; else len |= 0x05000000; iowrite32(len, atapi_reg); } /* Activate DMA */ ata_bmdma_start(qc); } /** * pdc2026x_bmdma_end - DMA engine stop * @qc: ATA command * * After a DMA completes we need to put the clock back to 33MHz for * PIO timings. * * Note: The host lock held by the libata layer protects * us from two channels both trying to set DMA bits at once */ static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct ata_device *adev = qc->dev; struct ata_taskfile *tf = &qc->tf; int sel66 = ap->port_no ? 0x08: 0x02; /* The clock bits are in the same register for both channels */ void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; void __iomem *clock = master + 0x11; void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); /* Cases the state machine will not complete correctly */ if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) { iowrite32(0, atapi_reg); iowrite8(ioread8(clock) & ~sel66, clock); } /* Flip back to 33Mhz for PIO */ if (adev->dma_mode > XFER_UDMA_2) iowrite8(ioread8(clock) & ~sel66, clock); ata_bmdma_stop(qc); pdc202xx_set_piomode(ap, adev); } /** * pdc2026x_dev_config - device setup hook * @adev: newly found device * * Perform chip specific early setup. We need to lock the transfer * sizes to 8bit to avoid making the state engine on the 2026x cards * barf. */ static void pdc2026x_dev_config(struct ata_device *adev) { adev->max_sectors = 256; } static int pdc2026x_port_start(struct ata_port *ap