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generated by cgit v1.2.3 (git 2.25.1) at 2024-09-10 08:14:41 +0000
class="o">*clk_hw), GFP_KERNEL); if (!clk_hw) return; clk_hw->hw.init = &init; init.name = clk_name; init.ops = ops; if (ops != &omap_gate_clkdm_clk_ops) { clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0); if (!clk_hw->enable_reg) goto cleanup; if (!of_property_read_u32(node, "ti,bit-shift", &val)) clk_hw->enable_bit = val; } clk_hw->ops = hw_ops; clk_hw->flags = MEMMAP_ADDRESSING; if (of_clk_get_parent_count(node) != 1) { pr_err("%s must have 1 parent\n", clk_name); goto cleanup; } parent_name = of_clk_get_parent_name(node, 0); init.parent_names = &parent_name; init.num_parents = 1; if (of_property_read_bool(node, "ti,set-rate-parent")) init.flags |= CLK_SET_RATE_PARENT; if (of_property_read_bool(node, "ti,set-bit-to-disable")) clk_hw->flags |= INVERT_ENABLE; clk = clk_register(NULL, &clk_hw->hw); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); return; } cleanup: kfree(clk_hw); } static void __init _of_ti_composite_gate_clk_setup(struct device_node *node, const struct clk_hw_omap_ops *hw_ops) { struct clk_hw_omap *gate; u32 val = 0; gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) return; gate->enable_reg = ti_clk_get_reg_addr(node, 0); if (!gate->enable_reg) goto cleanup; of_property_read_u32(node, "ti,bit-shift", &val); gate->enable_bit = val; gate->ops = hw_ops; gate->flags = MEMMAP_ADDRESSING; if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE)) return; cleanup: kfree(gate); } static void __init of_ti_composite_no_wait_gate_clk_setup(struct device_node *node) { _of_ti_composite_gate_clk_setup(node, NULL); } CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock", of_ti_composite_no_wait_gate_clk_setup); #ifdef CONFIG_ARCH_OMAP3 static void __init of_ti_composite_interface_clk_setup(struct device_node *node) { _of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait); } CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock", of_ti_composite_interface_clk_setup); #endif static void __init of_ti_composite_gate_clk_setup(struct device_node *node) { _of_ti_composite_gate_clk_setup(node, &clkhwops_wait); } CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock", of_ti_composite_gate_clk_setup); static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node) { _of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL); } CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock", of_ti_clkdm_gate_clk_setup); static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node) { _of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops, &clkhwops_wait); } CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock", of_ti_hsdiv_gate_clk_setup); static void __init of_ti_gate_clk_setup(struct device_node *node) { _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL); } CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup) static void __init of_ti_wait_gate_clk_setup(struct device_node *node) { _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait); } CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock", of_ti_wait_gate_clk_setup); #ifdef CONFIG_ARCH_OMAP3 static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node) { _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_am35xx_ipss_module_wait); } CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock", of_ti_am35xx_gate_clk_setup); static void __init of_ti_dss_gate_clk_setup(struct device_node *node) { _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_omap3430es2_dss_usbhost_wait); } CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock", of_ti_dss_gate_clk_setup); #endif