From 4bb90087d745c26401e09a3bd10137d7b05e9ea3 Mon Sep 17 00:00:00 2001
From: Andy Polyakov <appro@openssl.org>
Date: Fri, 27 May 2011 15:32:43 +0000
Subject: x86[_64]cpuid.pl: harmonize usage of reserved bits #20 and #30.

---
 crypto/rc4/asm/rc4-x86_64.pl | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

(limited to 'crypto/rc4/asm/rc4-x86_64.pl')

diff --git a/crypto/rc4/asm/rc4-x86_64.pl b/crypto/rc4/asm/rc4-x86_64.pl
index b08cc25656..44466ee97a 100755
--- a/crypto/rc4/asm/rc4-x86_64.pl
+++ b/crypto/rc4/asm/rc4-x86_64.pl
@@ -159,8 +159,8 @@ $code.=<<___;
 	movl	($dat,$XX[0],4),$TX[0]#d
 	test	\$-16,$len
 	jz	.Lloop1
-	bt	\$30,%r8d	# Intel CPU Family 6
-	jc	.L16x
+	bt	\$30,%r8d	# Intel CPU?
+	jc	.Lintel
 	and	\$7,$TX[1]
 	lea	1($XX[0]),$XX[1]
 	jz	.Loop8
@@ -217,7 +217,7 @@ $code.=<<___;
 	jmp	.Lexit
 
 .align	16
-.L16x:
+.Lintel:
 	test	\$-32,$len
 	jz	.Lloop1
 	and	\$15,$TX[1]
@@ -438,10 +438,8 @@ RC4_set_key:
 	xor	%r11,%r11
 
 	mov	OPENSSL_ia32cap_P(%rip),$idx#d
-	bt	\$20,$idx#d	# Intel CPU
-	jnc	.Lw1stloop
-	bt	\$30,$idx#d	# Intel CPU Family 6
-	jnc	.Lc1stloop
+	bt	\$20,$idx#d	# RC4_CHAR?
+	jc	.Lc1stloop
 	jmp	.Lw1stloop
 
 .align	16
-- 
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