From 58901bfaf9f195c9056bcc4986e7d2283373ddea Mon Sep 17 00:00:00 2001 From: Henry Brausen Date: Fri, 28 Jan 2022 01:53:07 -0700 Subject: Add clmul-based gmult for riscv64 with Zbb, Zbc ghash-riscv64.pl implements 128-bit galois field multiplication for use in the GCM mode using RISC-V carryless multiplication primitives. The clmul-accelerated routine can be selected by setting the Zbb and Zbc bits of the OPENSSL_riscvcap environment variable at runtime. Reviewed-by: Philipp Tomsich Signed-off-by: Henry Brausen Reviewed-by: Tomas Mraz Reviewed-by: Paul Dale (Merged from https://github.com/openssl/openssl/pull/17640) (cherry picked from commit 999376dcf33986c468361ede16fa9de409dc4e2e) --- crypto/modes/build.info | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'crypto/modes/build.info') diff --git a/crypto/modes/build.info b/crypto/modes/build.info index 0c0c9c3b80..792fff67b7 100644 --- a/crypto/modes/build.info +++ b/crypto/modes/build.info @@ -40,6 +40,9 @@ IF[{- !$disabled{asm} -}] $MODESASM_c64xplus=ghash-c64xplus.s $MODESDEF_c64xplus=GHASH_ASM + $MODESASM_riscv64=ghash-riscv64.s + $MODESDEF_riscv64=GHASH_ASM + # Now that we have defined all the arch specific variables, use the # appropriate one, and define the appropriate macros IF[$MODESASM_{- $target{asm_arch} -}] @@ -84,3 +87,4 @@ INCLUDE[aes-gcm-armv8-unroll8_64.o]=.. GENERATE[ghash-s390x.S]=asm/ghash-s390x.pl INCLUDE[ghash-s390x.o]=.. GENERATE[ghash-c64xplus.S]=asm/ghash-c64xplus.pl +GENERATE[ghash-riscv64.s]=asm/ghash-riscv64.pl -- cgit v1.2.3