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2023-10-26riscv: Add basic vector extension supportChristoph Müllner
The RISC-V vector extension comes with an implementation-defined number of bits per vector register (VLEN), which can be read out at run-time using the CSR 'vlenb' (which returns VLEN/8) followed by a multiplication by 8 (to convert bytes to bits). This patch introduces a RISC-V capability 'V' to specify the availability of the vector extension. If this extension is found at run-time, then we read out VLEN as described above and cache it. Caching ensures that we only read the CSR once at startup. This is necessary because reading out CSR can be expensive (e.g. if CSR readout is implemented using trap-and-emulate). Follow-up patches can make use of VLEN and chose the best strategy based on the available length of the vector registers. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
2022-05-19Add basic RISC-V cpuid and OPENSSL_riscvcapHenry Brausen
RISC-V cpuid implementation allows bitmanip extensions Zb[abcs] to be enabled at runtime using OPENSSL_riscvcap environment variable. For example, to specify 64-bit RISC-V with the G,C,Zba,Zbb,Zbc extensions, one could write: OPENSSL_riscvcap="rv64gc_zba_zbb_zbc" Architecture string parsing is still very primitive, but can be expanded in the future. Currently, only bitmanip extensions Zba, Zbb, Zbc and Zbs are supported. Includes implementation of constant-time CRYPTO_memcmp in riscv64 asm, as well as OPENSSL_cleanse. Assembly implementations are written using perlasm. Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Henry Brausen <henry.brausen@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> (Merged from https://github.com/openssl/openssl/pull/17640)