openssl - Mirror of https://github.com/openssl/openssl

Mirror of https://github.com/openssl/openssl

matthias

Age	Commit message (Expand)	Author
2002-07-08	oops, there were other cases of "ENGINE_ID" to change too.	Geoff Thorpe
2002-07-08	Correct an error in the README.ENGINE file.	Geoff Thorpe
2001-09-07	ispell	Ulf Möller
2001-09-04	Update the ENGINE README, and stock it up with extra verbeage for good	Geoff Thorpe
2000-11-07	Document that the Nuron hardware has been added and remove the	Richard Levitte
2000-10-27	-engine is gone.	Ulf Möller
2000-09-24	Change the Windows building scripts to enable DSO_WIN32.	Richard Levitte
2000-09-20	Add news and a description of the ENGINE part and how it's currently	Richard Levitte

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/*******************************************************************************

  Intel PRO/1000 Linux driver
  Copyright(c) 1999 - 2007 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include <linux/types.h>

struct e1000_hw;
struct e1000_adapter;

#include "defines.h"

#define er32(reg)	__er32(hw, E1000_##reg)
#define ew32(reg,val)	__ew32(hw, E1000_##reg, (val))
#define e1e_flush()	er32(STATUS)

#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
	(writel((value), ((a)->hw_addr + reg + ((offset) << 2))))

#define E1000_READ_REG_ARRAY(a, reg, offset) \
	(readl((a)->hw_addr + reg + ((offset) << 2)))

enum e1e_registers {
	E1000_CTRL     = 0x00000, /* Device Control - RW */
	E1000_STATUS   = 0x00008, /* Device Status - RO */
	E1000_EECD     = 0x00010, /* EEPROM/Flash Control - RW */
	E1000_EERD     = 0x00014, /* EEPROM Read - RW */
	E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
	E1000_FLA      = 0x0001C, /* Flash Access - RW */
	E1000_MDIC     = 0x00020, /* MDI Control - RW */
	E1000_SCTL     = 0x00024, /* SerDes Control - RW */
	E1000_FCAL     = 0x00028, /* Flow Control Address Low - RW */
	E1000_FCAH     = 0x0002C, /* Flow Control Address High -RW */
	E1000_FEXTNVM  = 0x00028, /* Future Extended NVM - RW */
	E1000_FCT      = 0x00030, /* Flow Control Type - RW */
	E1000_VET      = 0x00038, /* VLAN Ether Type - RW */
	E1000_ICR      = 0x000C0, /* Interrupt Cause Read - R/clr */
	E1000_ITR      = 0x000C4, /* Interrupt Throttling Rate - RW */
	E1000_ICS      = 0x000C8, /* Interrupt Cause Set - WO */
	E1000_IMS      = 0x000D0, /* Interrupt Mask Set - RW */
	E1000_IMC      = 0x000D8, /* Interrupt Mask Clear - WO */
	E1000_IAM      = 0x000E0, /* Interrupt Acknowledge Auto Mask */
	E1000_RCTL     = 0x00100, /* RX Control - RW */
	E1000_FCTTV    = 0x00170, /* Flow Control Transmit Timer Value - RW */
	E1000_TXCW     = 0x00178, /* TX Configuration Word - RW */
	E1000_RXCW     = 0x00180, /* RX Configuration Word - RO */
	E1000_TCTL     = 0x00400, /* TX Control - RW */
	E1000_TCTL_EXT = 0x00404, /* Extended TX Control - RW */
	E1000_TIPG     = 0x00410, /* TX Inter-packet gap -RW */
	E1000_AIT      = 0x00458, /* Adaptive Interframe Spacing Throttle - RW */
	E1000_LEDCTL   = 0x00E00, /* LED Control - RW */
	E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
	E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
	E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
	E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
	E1000_PBS      = 0x01008, /* Packet Buffer Size */
	E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
	E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
	E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
	E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
	E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
	E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */
	E1000_PSRCTL   = 0x02170, /* Packet Split Receive Control - RW */
	E1000_RDBAL    = 0x02800, /* RX Descriptor Base Address Low - RW */
	E1000_RDBAH    = 0x02804, /* RX Descriptor Base Address High - RW */
	E1000_RDLEN    = 0x02808, /* RX Descriptor Length - RW */
	E1000_RDH      = 0x02810, /* RX Descriptor Head - RW */
	E1000_RDT      = 0x02818, /* RX Descriptor Tail - RW */
	E1000_RDTR     = 0x02820, /* RX Delay Timer - RW */
	E1000_RADV     = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */

/* Convenience macros
 *
 * Note: "_n" is the queue number of the register to be written to.
 *
 * Example usage:
 * E1000_RDBAL_REG(current_rx_queue)
 *
 */
#define E1000_RDBAL_REG(_n)   (E1000_RDBAL + (_n << 8))
	E1000_KABGTXD  = 0x03004, /* AFE Band Gap Transmit Ref Data */
	E1000_TDBAL    = 0x03800, /* TX Descriptor Base Address Low - RW */
	E1000_TDBAH    = 0x03804, /* TX Descriptor Base Address High - RW */
	E1000_TDLEN    = 0x03808, /* TX Descriptor Length - RW */
	E1000_TDH      = 0x03810, /* TX Descriptor Head - RW */
	E1000_TDT      = 0x03818, /* TX Descriptor Tail - RW */
	E1000_TIDV     = 0x03820, /* TX Interrupt Delay Value - RW */
	E1000_TXDCTL   = 0x03828, /* TX Descriptor Control - RW */
	E1000_TADV     = 0x0382C, /* TX Interrupt Absolute Delay Val - RW */
	E1000_TARC0    = 0x03840, /* TX Arbitration Count (0) */
	E1000_TXDCTL1  = 0x03928, /* TX Descriptor Control (1) - RW */
	E1000_TARC1    = 0x03940, /* TX Arbitration Count (1) */
	E1000_CRCERRS  = 0x04000, /* CRC Error Count - R/clr */
	E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
	E1000_SYMERRS  = 0x04008, /* Symbol Error Count - R/clr */
	E1000_RXERRC   = 0x0400C, /* Receive Error Count - R/clr */
	E1000_MPC      = 0x04010, /* Missed Packet Count - R/clr */
	E1000_SCC      = 0x04014, /* Single Collision Count - R/clr */
	E1000_ECOL     = 0x04018, /* Excessive Collision Count - R/clr */
	E1000_MCC      = 0x0401C, /* Multiple Collision Count - R/clr */
	E1000_LATECOL  = 0x04020, /* Late Collision Count - R/clr */
	E1000_COLC     = 0x04028, /* Collision Count - R/clr */
	E1000_DC       = 0x04030, /* Defer Count - R/clr */
	E1000_TNCRS    = 0x04034, /* TX-No CRS - R/clr */
	E1000_SEC      = 0x04038, /* Sequence Error Count - R/clr */
	E1000_CEXTERR  = 0x0403C, /* Carrier Extension Error Count - R/clr */
	E1000_RLEC     = 0x04040, /* Receive Length Error Count - R/clr */
	E1000_XONRXC   = 0x04048, /* XON RX Count - R/clr */
	E1000_XONTXC   = 0x0404C, /* XON TX Count - R/clr */
	E1000_XOFFRXC  = 0x04050, /* XOFF RX Count - R/clr */
	E1000_XOFFTXC  = 0x04054, /* XOFF TX Count - R/clr */
	E1000_FCRUC    = 0x04058, /* Flow Control RX Unsupported Count- R/clr */
	E1000_PRC64    = 0x0405C, /* Packets RX (64 bytes) - R/clr */
	E1000_PRC127   = 0x04060, /* Packets RX (65-127 bytes) - R/clr */
	E1000_PRC255   = 0x04064, /* Packets RX (128-255 bytes) - R/clr */
	E1000_PRC511   = 0x04068, /* Packets RX (255-511 bytes) - R/clr */
	E1000_PRC1023  = 0x0406C, /* Packets RX (512-1023 bytes) - R/clr */
	E1000_PRC1522  = 0x04070, /* Packets RX (1024-1522 bytes) - R/clr */
	E1000_GPRC     = 0x04074, /* Good Packets RX Count - R/clr */
	E1000_BPRC     = 0x04078, /* Broadcast Packets RX Count - R/clr */
	E1000_MPRC     = 0x0407C, /* Multicast Packets RX Count - R/clr */
	E1000_GPTC     = 0x04080, /* Good Packets TX Count - R/clr */
	E1000_GORCL    =</