diff options
author | Andy Polyakov <appro@openssl.org> | 2007-04-01 17:28:08 +0000 |
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committer | Andy Polyakov <appro@openssl.org> | 2007-04-01 17:28:08 +0000 |
commit | 162f677def843739f4984d674b4ad33eb726e7ea (patch) | |
tree | 73897035de9fdcf42991bb2530f488a6ca1663df /doc/crypto | |
parent | 287546242539e686ef1233d0a7c57c935fb61c3f (diff) |
Update x86cpuid.pl to correctly detect shared cache and to support new
RC4_set_key.
Diffstat (limited to 'doc/crypto')
-rw-r--r-- | doc/crypto/OPENSSL_ia32cap.pod | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/doc/crypto/OPENSSL_ia32cap.pod b/doc/crypto/OPENSSL_ia32cap.pod index 03ac6e6834..2e659d34a5 100644 --- a/doc/crypto/OPENSSL_ia32cap.pod +++ b/doc/crypto/OPENSSL_ia32cap.pod @@ -17,20 +17,27 @@ register after executing CPUID instruction with EAX=1 input value (see Intel Application Note #241618). Naturally it's meaningful on IA-32[E] platforms only. The variable is normally set up automatically upon toolkit initialization, but can be manipulated afterwards to modify -crypto library behaviour. For the moment of this writing five bits are -significant, namely bit #28 denoting Hyperthreading, which is used to -distinguish Intel P4 core, bit #26 denoting SSE2 support, bit #25 -denoting SSE support, bit #23 denoting MMX support, and bit #4 denoting -presence of Time-Stamp Counter. Clearing bit #26 at run-time for -example disables high-performance SSE2 code present in the crypto -library. You might have to do this if target OpenSSL application is -executed on SSE2 capable CPU, but under control of OS which does not -support SSE2 extentions. Even though you can manipulate the value -programmatically, you most likely will find it more appropriate to set -up an environment variable with the same name prior starting target -application, e.g. 'env OPENSSL_ia32cap=0x12800010 apps/openssl', to -achieve same effect without modifying the application source code. -Alternatively you can reconfigure the toolkit with no-sse2 option and -recompile. +crypto library behaviour. For the moment of this writing six bits are +significant, namely: + +1. bit #28 denoting Hyperthreading, which is used to distiguish + cores with shared cache; +2. bit #26 denoting SSE2 support; +3. bit #25 denoting SSE support; +4. bit #23 denoting MMX support; +5. bit #20, reserved by Intel, is used to choose between RC4 code + pathes; +6. bit #4 denoting presence of Time-Stamp Counter. + +For example, clearing bit #26 at run-time disables high-performance +SSE2 code present in the crypto library. You might have to do this if +target OpenSSL application is executed on SSE2 capable CPU, but under +control of OS which does not support SSE2 extentions. Even though you +can manipulate the value programmatically, you most likely will find it +more appropriate to set up an environment variable with the same name +prior starting target application, e.g. on Intel P4 processor 'env +OPENSSL_ia32cap=0x12900010 apps/openssl', to achieve same effect +without modifying the application source code. Alternatively you can +reconfigure the toolkit with no-sse2 option and recompile. =cut |