diff options
author | Andy Polyakov <appro@openssl.org> | 2015-03-03 21:44:53 +0100 |
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committer | Andy Polyakov <appro@openssl.org> | 2015-03-08 14:09:32 +0100 |
commit | e390ae50e0bc41676994c6fa23f7b65a8afc4d7f (patch) | |
tree | 690a3282ce5500dabab42d6f7b004c8496df37a3 /crypto/sha | |
parent | 63a3c45582670f1f2d8e0df3835e9bd81c34d137 (diff) |
ARMv4 assembly pack: add Cortex-A15 performance data.
Reviewed-by: Tim Hudson <tjh@openssl.org>
Diffstat (limited to 'crypto/sha')
-rw-r--r-- | crypto/sha/asm/sha1-armv4-large.pl | 4 | ||||
-rw-r--r-- | crypto/sha/asm/sha512-armv4.pl | 13 |
2 files changed, 6 insertions, 11 deletions
diff --git a/crypto/sha/asm/sha1-armv4-large.pl b/crypto/sha/asm/sha1-armv4-large.pl index b2c30322c3..61307b7c61 100644 --- a/crypto/sha/asm/sha1-armv4-large.pl +++ b/crypto/sha/asm/sha1-armv4-large.pl @@ -60,7 +60,9 @@ # is ~2.5x larger and there are some redundant instructions executed # when processing last block, improvement is not as big for smallest # blocks, only ~30%. Snapdragon S4 is a tad faster, 6.4 cycles per -# byte, which is also >80% faster than integer-only code. +# byte, which is also >80% faster than integer-only code. Cortex-A15 +# is even faster spending 5.6 cycles per byte outperforming integer- +# only code by factor of 2. # May 2014. # diff --git a/crypto/sha/asm/sha512-armv4.pl b/crypto/sha/asm/sha512-armv4.pl index fb7dc506ac..daab297db5 100644 --- a/crypto/sha/asm/sha512-armv4.pl +++ b/crypto/sha/asm/sha512-armv4.pl @@ -34,16 +34,9 @@ # terms it's 22.6 cycles per byte, which is disappointing result. # Technical writers asserted that 3-way S4 pipeline can sustain # multiple NEON instructions per cycle, but dual NEON issue could -# not be observed, and for NEON-only sequences IPC(*) was found to -# be limited by 1:-( 0.33 and 0.66 were measured for sequences with -# ILPs(*) of 1 and 2 respectively. This in turn means that you can -# even find yourself striving, as I did here, for achieving IPC -# adequate to one delivered by Cortex A8 [for reference, it's -# 0.5 for ILP of 1, and 1 for higher ILPs]. -# -# (*) ILP, instruction-level parallelism, how many instructions -# *can* execute at the same time. IPC, instructions per cycle, -# indicates how many instructions actually execute. +# not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html +# for further details. On side note Cortex-A15 processes one byte in +# 16 cycles. # Byte order [in]dependence. ========================================= # |