diff options
| author | Andy Polyakov <appro@openssl.org> | 2009-02-09 16:03:33 +0000 |
|---|---|---|
| committer | Andy Polyakov <appro@openssl.org> | 2009-02-09 16:03:33 +0000 |
| commit | 7012d2a8fa83db995f833ec1784b422e480b8179 (patch) | |
| tree | 473c66903f534909bfd6d7a82a5c34df12c8f345 /crypto/sha | |
| parent | 8626230a0227b15c0e0542f5a65f802ee32772b6 (diff) | |
sha1-sparcv9a.pl: fix bug in commentary section.
Diffstat (limited to 'crypto/sha')
| -rw-r--r-- | crypto/sha/asm/sha1-sparcv9a.pl | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/crypto/sha/asm/sha1-sparcv9a.pl b/crypto/sha/asm/sha1-sparcv9a.pl index 6902b52b24..be7da91e48 100644 --- a/crypto/sha/asm/sha1-sparcv9a.pl +++ b/crypto/sha/asm/sha1-sparcv9a.pl @@ -112,8 +112,9 @@ ___ # virtually uniform performance of ~9.3 cycles per SHA1 round. Timings # mentioned above are theoretical lower limits. Real-life performance # was measured to be 6.6 cycles per SHA1 round on USIIi and 8.3 on -# USIII. The latter means that processor manual must have an error in -# instruction latency table or there is some unmentioned shortcut... +# USIII. The latter is lower than half-round VIS timing, because there +# are 16 Xupdate-free rounds, which "push down" average theoretical +# timing to 8 cycles... } # The reference Xupdate procedure is then "strained" over *pairs* of |