diff options
author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-01-18 13:16:26 +0100 |
---|---|---|
committer | Hugo Landau <hlandau@openssl.org> | 2023-10-26 15:55:49 +0100 |
commit | 5191bcc81650c34a4660a0921124e4195e18e4b0 (patch) | |
tree | a4eef529d39b68179321cd706bf63d02cfca78dc /crypto/perlasm | |
parent | 003f5698146b81f3185d7f17d60a7351c69e236d (diff) |
riscv: GCM: Provide a Zvkg-based implementation
The upcoming RISC-V vector crypto extensions feature
a Zvkg extension, that provides a vghmac.vv instruction.
This patch provides an implementation that utilizes this
extension if available.
Tested on QEMU and no regressions observed.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Hugo Landau <hlandau@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/21923)
Diffstat (limited to 'crypto/perlasm')
-rw-r--r-- | crypto/perlasm/riscv.pm | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/crypto/perlasm/riscv.pm b/crypto/perlasm/riscv.pm index 8443f6c29c..7700bf6429 100644 --- a/crypto/perlasm/riscv.pm +++ b/crypto/perlasm/riscv.pm @@ -281,6 +281,14 @@ sub rev8 { # Vector instructions +sub vle32_v { + # vle32.v vd, (rs1) + my $template = 0b0000001_00000_00000_110_00000_0000111; + my $vd = read_vreg shift; + my $rs1 = read_reg shift; + return ".word ".($template | ($rs1 << 15) | ($vd << 7)); +} + sub vle64_v { # vle64.v vd, (rs1) my $template = 0b0000001_00000_00000_111_00000_0000111; @@ -332,6 +340,14 @@ sub vor_vv_v0t { return ".word ".($template | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7)); } +sub vse32_v { + # vse32.v vd, (rs1) + my $template = 0b0000001_00000_00000_110_00000_0100111; + my $vd = read_vreg shift; + my $rs1 = read_reg shift; + return ".word ".($template | ($rs1 << 15) | ($vd << 7)); +} + sub vse64_v { # vse64.v vd, (rs1) my $template = 0b0000001_00000_00000_111_00000_0100111; @@ -345,6 +361,11 @@ sub vsetivli__x0_2_e64_m1_tu_mu { return ".word 0xc1817057"; } +sub vsetivli__x0_4_e32_m1_tu_mu { + # vsetivli x0, 4, e32, m1, tu, mu + return ".word 0xc1027057"; +} + sub vslidedown_vi { # vslidedown.vi vd, vs2, uimm my $template = 0b0011111_00000_00000_011_00000_1010111; @@ -458,4 +479,23 @@ sub vclmul_vx { return ".word ".($template | ($vs2 << 20) | ($rs1 << 15) | ($vd << 7)); } +## Zvkg instructions + +sub vghsh_vv { + # vghsh.vv vd, vs2, vs1 + my $template = 0b1011001_00000_00000_010_00000_1110111; + my $vd = read_vreg shift; + my $vs2 = read_vreg shift; + my $vs1 = read_vreg shift; + return ".word ".($template | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7)); +} + +sub vgmul_vv { + # vgmul.vv vd, vs2 + my $template = 0b1010001_00000_10001_010_00000_1110111; + my $vd = read_vreg shift; + my $vs2 = read_vreg shift; + return ".word ".($template | ($vs2 << 20) | ($vd << 7)); +} + 1; |