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author | Henry Brausen <henry.brausen@vrull.eu> | 2022-01-28 01:28:52 -0700 |
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committer | Tomas Mraz <tomas@openssl.org> | 2022-11-21 10:49:52 +0100 |
commit | 8448432a3be6cd5eb2576594c742e3d54d92f78a (patch) | |
tree | 59b96ecce2d8dbf89a1ec07af702a6e7757a8505 /crypto/modes/build.info | |
parent | b60603c5e3ac6396306bbaafd829f8340d22e1a0 (diff) |
Add basic RISC-V cpuid and OPENSSL_riscvcap
RISC-V cpuid implementation allows bitmanip extensions Zb[abcs] to
be enabled at runtime using OPENSSL_riscvcap environment variable.
For example, to specify 64-bit RISC-V with the G,C,Zba,Zbb,Zbc
extensions, one could write: OPENSSL_riscvcap="rv64gc_zba_zbb_zbc"
Architecture string parsing is still very primitive, but can be
expanded in the future. Currently, only bitmanip extensions Zba, Zbb,
Zbc and Zbs are supported.
Includes implementation of constant-time CRYPTO_memcmp in riscv64 asm,
as well as OPENSSL_cleanse. Assembly implementations are written using
perlasm.
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Henry Brausen <henry.brausen@vrull.eu>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/17640)
(cherry picked from commit 360f6dcc5aa1a86ec3ff9a94612b88e3d960ee2e)
Diffstat (limited to 'crypto/modes/build.info')
0 files changed, 0 insertions, 0 deletions