diff options
| author | Josh Soref <jsoref@users.noreply.github.com> | 2017-11-11 19:03:10 -0500 |
|---|---|---|
| committer | Rich Salz <rsalz@openssl.org> | 2017-11-11 19:03:10 -0500 |
| commit | 46f4e1bec51dc96fa275c168752aa34359d9ee51 (patch) | |
| tree | c80b737d1fff479fd88f6c41175187ebad868299 /crypto/camellia | |
| parent | b4d0fa49d9d1a43792e58b0c8066bb23b9e53ef4 (diff) | |
Many spelling fixes/typo's corrected.
Around 138 distinct errors found and fixed; thanks!
Reviewed-by: Kurt Roeckx <kurt@roeckx.be>
Reviewed-by: Tim Hudson <tjh@openssl.org>
Reviewed-by: Rich Salz <rsalz@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/3459)
Diffstat (limited to 'crypto/camellia')
| -rw-r--r-- | crypto/camellia/asm/cmllt4-sparcv9.pl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/crypto/camellia/asm/cmllt4-sparcv9.pl b/crypto/camellia/asm/cmllt4-sparcv9.pl index 50bddfed29..6396679a5a 100644 --- a/crypto/camellia/asm/cmllt4-sparcv9.pl +++ b/crypto/camellia/asm/cmllt4-sparcv9.pl @@ -17,7 +17,7 @@ # Camellia for SPARC T4. # # As with AES below results [for aligned data] are virtually identical -# to critical path lenths for 3-cycle instruction latency: +# to critical path lengths for 3-cycle instruction latency: # # 128-bit key 192/256- # CBC encrypt 4.14/4.21(*) 5.46/5.52 @@ -25,7 +25,7 @@ # misaligned data. # # As with Intel AES-NI, question is if it's possible to improve -# performance of parallelizeable modes by interleaving round +# performance of parallelizable modes by interleaving round # instructions. In Camellia every instruction is dependent on # previous, which means that there is place for 2 additional ones # in between two dependent. Can we expect 3x performance improvement? |