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authorAndy Polyakov <appro@openssl.org>2015-11-04 23:57:06 +0100
committerAndy Polyakov <appro@openssl.org>2015-11-16 13:07:33 +0100
commit817ddb9fb07e78b451e838a77b2b272b0dd23e5f (patch)
tree3802d1403b82136ffbce77c905f6217bc42377b0 /crypto/aes
parentf236ef27bd2ca99b3367554aa3e2fc9ca345deb5 (diff)
aesni-sha256-x86_64.pl: fix crash on AMD Jaguar.
It was also found that stich performs suboptimally on AMD Jaguar, hence execution is limited to XOP-capable and Intel processors. Reviewed-by: Kurt Roeckx <kurt@openssl.org> (cherry picked from commit a5fd24d19bbb586b1c6d235c2021e9bead22c9f5)
Diffstat (limited to 'crypto/aes')
-rw-r--r--crypto/aes/asm/aesni-sha256-x86_64.pl7
1 files changed, 2 insertions, 5 deletions
diff --git a/crypto/aes/asm/aesni-sha256-x86_64.pl b/crypto/aes/asm/aesni-sha256-x86_64.pl
index 19b0433b3b..1772cbe9cc 100644
--- a/crypto/aes/asm/aesni-sha256-x86_64.pl
+++ b/crypto/aes/asm/aesni-sha256-x86_64.pl
@@ -139,11 +139,8 @@ $code.=<<___ if ($avx>1);
je ${func}_avx2
___
$code.=<<___;
- and \$`1<<30`,%eax # mask "Intel CPU" bit
- and \$`1<<28|1<<9`,%r10d # mask AVX+SSSE3 bits
- or %eax,%r10d
- cmp \$`1<<28|1<<9|1<<30`,%r10d
- je ${func}_avx
+ and \$`1<<28`,%r10d # check for AVX
+ jnz ${func}_avx
ud2
___
}