summaryrefslogtreecommitdiffstats
path: root/Configurations
diff options
context:
space:
mode:
authorRichard Levitte <levitte@openssl.org>2019-06-16 22:17:26 +0200
committerRichard Levitte <levitte@openssl.org>2019-06-17 16:08:53 +0200
commita9bb7e9270d26416cc387bc0777c18f9690e2302 (patch)
tree22122cf1ecb08ea4e957e3e2256dacad1e1b17c7 /Configurations
parent94707b0b68a16e806d27a06d9297732045319197 (diff)
Move modes_asm_src file information to build.info files
Reviewed-by: Matt Caswell <matt@openssl.org> (Merged from https://github.com/openssl/openssl/pull/9166)
Diffstat (limited to 'Configurations')
-rw-r--r--Configurations/00-base-templates.conf11
-rw-r--r--Configurations/10-main.conf2
-rw-r--r--Configurations/README3
3 files changed, 0 insertions, 16 deletions
diff --git a/Configurations/00-base-templates.conf b/Configurations/00-base-templates.conf
index 168d776ba1..5c73ce35ad 100644
--- a/Configurations/00-base-templates.conf
+++ b/Configurations/00-base-templates.conf
@@ -14,7 +14,6 @@ my %targets=(
thread_scheme => "(unknown)", # Assume we don't know
thread_defines => [],
- modes_asm_src => "",
padlock_asm_src => "",
chacha_asm_src => "chacha_enc.c",
poly1305_asm_src => "",
@@ -155,7 +154,6 @@ my %targets=(
x86_asm => {
template => 1,
- modes_asm_src => "ghash-x86.s",
padlock_asm_src => "e_padlock-x86.s",
chacha_asm_src => "chacha-x86.s",
poly1305_asm_src=> "poly1305-x86.s",
@@ -166,7 +164,6 @@ my %targets=(
},
x86_64_asm => {
template => 1,
- modes_asm_src => "ghash-x86_64.s aesni-gcm-x86_64.s",
padlock_asm_src => "e_padlock-x86_64.s",
chacha_asm_src => "chacha-x86_64.s",
poly1305_asm_src=> "poly1305-x86_64.s",
@@ -174,13 +171,11 @@ my %targets=(
},
ia64_asm => {
template => 1,
- modes_asm_src => "ghash-ia64.s",
chacha_asm_src => "chacha-ia64.S",
poly1305_asm_src=> "asm/poly1305-ia64.S",
},
sparcv9_asm => {
template => 1,
- modes_asm_src => "ghash-sparcv9.S",
poly1305_asm_src=> "poly1305-sparcv9.S",
},
sparcv8_asm => {
@@ -188,7 +183,6 @@ my %targets=(
},
alpha_asm => {
template => 1,
- modes_asm_src => "ghash-alpha.S",
},
mips32_asm => {
template => 1,
@@ -200,28 +194,24 @@ my %targets=(
},
s390x_asm => {
template => 1,
- modes_asm_src => "ghash-s390x.S",
chacha_asm_src => "chacha-s390x.S",
poly1305_asm_src=> "poly1305-s390x.S",
keccak1600_asm_src => "keccak1600-s390x.S",
},
armv4_asm => {
template => 1,
- modes_asm_src => "ghash-armv4.S ghashv8-armx.S",
chacha_asm_src => "chacha-armv4.S",
poly1305_asm_src=> "poly1305-armv4.S",
keccak1600_asm_src => "keccak1600-armv4.S",
},
aarch64_asm => {
template => 1,
- modes_asm_src => "ghashv8-armx.S",
chacha_asm_src => "chacha-armv8.S",
poly1305_asm_src=> "poly1305-armv8.S",
keccak1600_asm_src => "keccak1600-armv8.S",
},
parisc11_asm => {
template => 1,
- modes_asm_src => "ghash-parisc.s",
},
parisc20_64_asm => {
template => 1,
@@ -229,7 +219,6 @@ my %targets=(
},
ppc32_asm => {
template => 1,
- modes_asm_src => "ghashp8-ppc.s",
chacha_asm_src => "chacha-ppc.s",
poly1305_asm_src=> "poly1305-ppc.s poly1305-ppcfp.s",
},
diff --git a/Configurations/10-main.conf b/Configurations/10-main.conf
index 2895eef4fe..450fe0dcb8 100644
--- a/Configurations/10-main.conf
+++ b/Configurations/10-main.conf
@@ -949,7 +949,6 @@ my %targets = (
cppflags => combine("-DOPENSSL_SMALL_FOOTPRINT",
threads("-D_REENTRANT")),
bn_ops => "BN_LLONG",
- modes_asm_src => "ghash-c64xplus.s",
chacha_asm_src => "chacha-c64xplus.s",
poly1305_asm_src => "poly1305-c64xplus.s",
thread_scheme => "pthreads",
@@ -1852,7 +1851,6 @@ my %targets = (
perlasm_scheme => 'ias',
pointer_size => "",
- modes_asm_src => "", # Because ghash-ia64.s doesn't work on VMS
},
"vms-ia64-p32" => {
inherit_from => [ "vms-ia64" ],
diff --git a/Configurations/README b/Configurations/README
index 664e8d86bd..84e7b20c7d 100644
--- a/Configurations/README
+++ b/Configurations/README
@@ -240,9 +240,6 @@ In each table entry, the following keys are significant:
export vars as
accessor functions.
- modes_asm_src => Assembler implementation of cipher modes,
- currently the functions gcm_gmult_4bit and
- gcm_ghash_4bit.
padlock_asm_src => Assembler implementation of core parts of
the padlock engine. This is mandatory on
any platform where the padlock engine might