diff options
author | Xiaokang Qian <xiaokang.qian@arm.com> | 2023-01-29 06:22:43 +0000 |
---|---|---|
committer | Tomas Mraz <tomas@openssl.org> | 2023-02-08 16:54:57 +0100 |
commit | 513e103f14e8473fb6810aa216ab3fb7b724ca5d (patch) | |
tree | d3f0c0b8195b4bb22d611c697a28a33d94c791e5 | |
parent | 79040cf29e011c21789563d74da626b7465a0540 (diff) |
Apply aes-gcm unroll8+eor3 optimization patch to Neoverse V2
Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/20184)
-rw-r--r-- | crypto/arm_arch.h | 1 | ||||
-rw-r--r-- | crypto/armcap.c | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h index a77a7bacb5..cc5cc5ba49 100644 --- a/crypto/arm_arch.h +++ b/crypto/arm_arch.h @@ -104,6 +104,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized; # define ARM_CPU_PART_V1 0xD40 # define ARM_CPU_PART_N2 0xD49 # define HISI_CPU_PART_KP920 0xD01 +# define ARM_CPU_PART_V2 0xD4F # define MIDR_PARTNUM_SHIFT 4 # define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT) diff --git a/crypto/armcap.c b/crypto/armcap.c index 68f735baec..01b3b32534 100644 --- a/crypto/armcap.c +++ b/crypto/armcap.c @@ -400,7 +400,8 @@ void OPENSSL_cpuid_setup(void) OPENSSL_armv8_rsa_neonized = 1; } if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) || - MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2)) && + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) && (OPENSSL_armcap_P & ARMV8_SHA3)) OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3; # endif |