/*
* STMicroelectronics STM32 SPI Controller driver (master mode only)
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
*
* License terms: GPL V2.0.
*
* spi_stm32 driver is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* spi_stm32 driver is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License along with
* spi_stm32 driver. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/debugfs.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>
#define DRIVER_NAME "spi_stm32"
/* STM32 SPI registers */
#define STM32_SPI_CR1 0x00
#define STM32_SPI_CR2 0x04
#define STM32_SPI_CFG1 0x08
#define STM32_SPI_CFG2 0x0C
#define STM32_SPI_IER 0x10
#define STM32_SPI_SR 0x14
#define STM32_SPI_IFCR 0x18
#define STM32_SPI_TXDR 0x20
#define STM32_SPI_RXDR 0x30
#define STM32_SPI_I2SCFGR 0x50
/* STM32_SPI_CR1 bit fields */
#define SPI_CR1_SPE BIT(0)
#define SPI_CR1_MASRX BIT(8)
#define SPI_CR1_CSTART BIT(9)
#define SPI_CR1_CSUSP BIT(10)
#define SPI_CR1_HDDIR BIT(11)
#define SPI_CR1_SSI BIT(12)
/* STM32_SPI_CR2 bit fields */
#define SPI_CR2_TSIZE_SHIFT 0
#define SPI_CR2_TSIZE GENMASK(15, 0)
/* STM32_SPI_CFG1 bit fields */
#define SPI_CFG1_DSIZE_SHIFT 0
#define SPI_CFG1_DSIZE GENMASK(4, 0)
#define SPI_CFG1_FTHLV_SHIFT 5
#define SPI_CFG1_FTHLV GENMASK(8, 5)
#define SPI_CFG1_RXDMAEN BIT(14)
#define SPI_CFG1_TXDMAEN BIT(15)
#define SPI_CFG1_MBR_SHIFT 28
#define SPI_CFG1_MBR GENMASK(30, 28)
#define SPI_CFG1_MBR_MIN 0
#define SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
/* STM32_SPI_CFG2 bit fields */
#define SPI_CFG2_MIDI_SHIFT 4
#define SPI_CFG2_MIDI GENMASK(7, 4)
#define SPI_CFG2_COMM_SHIFT 17
#define SPI_CFG2_COMM GENMASK(18, 17)
#define SPI_CFG2_SP_SHIFT 19
#define SPI_CFG2_SP GENMASK(21, 19)
#define SPI_CFG2_MASTER BIT(22)
#define SPI_CFG2_LSBFRST BIT(23)
#define SPI_CFG2_CPHA BIT(24)
#define SPI_CFG2_CPOL BIT(25)
#define SPI_CFG2_SSM BIT(26)
#define SPI_CFG2_AFCNTR BIT(31)
/* STM32_SPI_IER bit fields */
#define SPI_IER_RXPIE BIT(0)
#define SPI_IER_TXPIE BIT(1)
#define SPI_IER_DXPIE BIT(2)
#define SPI_IER_EOTIE BIT(3)
#define SPI_IER_TXTFIE BIT(4)
#define SPI_IER_OVRIE BIT(6)
#define SPI_IER_MODFIE BIT(9)
#define SPI_IER_ALL GENMASK(10, 0)
/* STM32_SPI_SR bit fields */
#define SPI_SR_RXP BIT(0)
#define SPI_SR_TXP BIT(1)
#define SPI_SR_EOT BIT(3)
#define SPI_SR_OVR BIT(6)
#define SPI_SR_MODF BIT(9)
#define SPI_SR_SUSP BIT(11)
#define SPI_SR_RXPLVL_SHIFT 13
#define SPI_SR_RXPLVL GENMASK(14, 13)
#define SPI_SR_RXWNE BIT(15)
/* STM32_SPI_IFCR bit fields */
#define SPI_IFCR_ALL GENMASK(11, 3)
/* STM32_SPI_I2SCFGR bit fields */
#define SPI_I2SCFGR_I2SMOD BIT(0)
/* SPI Master Baud Rate min/max divisor */
#define SPI_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
#define SPI_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
/* SPI Communication mode */
#define SPI_FULL_DUPLEX 0
#define SPI_SIMPLEX_TX 1
#define SPI_SIMPLEX_RX 2
#define SPI_HALF_DUPLEX 3
#define SPI_1HZ_NS 1000000000
/**
* struct stm32_spi - private data of the SPI controller
* @dev: driver model representation of the controller
* @master: controller master interface
* @base: virtual memory area
* @clk: hw kernel clock feeding the SPI clock generator
* @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
* @rst: SPI controller reset line
* @lock: prevent I/O concurrent access
* @irq: SPI controller interrupt line
* @fifo_size: size of the embedded fifo in bytes
* @cur_midi: master inter-data idleness in ns
* @cur_speed: speed configured in Hz
* @cur_bpw: number of bits in a single SPI data frame
* @cur_fthlv: fifo threshold level (data frames in a single data packet)
* @cur_comm: SPI communication mode
* @cur_xferlen: current transfer length in bytes
* @cur_usedma: boolean to know if dma is used in current transfer
* @tx_buf: data to be written, or NULL
* @rx_buf: data to be read, or NULL
* @tx_len: number of data to be written in bytes
* @rx_len: number of data to be read in bytes
* @dma_tx: dma channel for TX transfer
* @dma_rx: dma channel for RX transfer
* @phys_addr: SPI registers physical base address
*/
struct stm32_spi {
struct device *dev;
struct spi_master *master;
void __iomem *base;
struct clk *clk;
u32 clk_rate;
struct reset_control *rst;
spinlock_t lock; /* prevent I/O concurrent access */
int irq;
unsigned int fifo_size;
unsigned int cur_midi;