1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
|
/*
* Copyright (C) 2017 Spreadtrum Communications Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <linux/hwspinlock.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/sizes.h>
/* Registers definitions for ADI controller */
#define REG_ADI_CTRL0 0x4
#define REG_ADI_CHN_PRIL 0x8
#define REG_ADI_CHN_PRIH 0xc
#define REG_ADI_INT_EN 0x10
#define REG_ADI_INT_RAW 0x14
#define REG_ADI_INT_MASK 0x18
#define REG_ADI_INT_CLR 0x1c
#define REG_ADI_GSSI_CFG0 0x20
#define REG_ADI_GSSI_CFG1 0x24
#define REG_ADI_RD_CMD 0x28
#define REG_ADI_RD_DATA 0x2c
#define REG_ADI_ARM_FIFO_STS 0x30
#define REG_ADI_STS 0x34
#define REG_ADI_EVT_FIFO_STS 0x38
#define REG_ADI_ARM_CMD_STS 0x3c
#define REG_ADI_CHN_EN 0x40
#define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
#define REG_ADI_CHN_EN1 0x20c
/* Bits definitions for register REG_ADI_GSSI_CFG0 */
#define BIT_CLK_ALL_ON BIT(30)
/* Bits definitions for register REG_ADI_RD_DATA */
#define BIT_RD_CMD_BUSY BIT(31)
#define RD_ADDR_SHIFT 16
#define RD_VALUE_MASK GENMASK(15, 0)
#define RD_ADDR_MASK GENMASK(30, 16)
/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
#define BIT_FIFO_FULL BIT(11)
#define BIT_FIFO_EMPTY BIT(10)
/*
* ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
* The slave devices address offset is always 0x8000 and size is 4K.
*/
#define ADI_SLAVE_ADDR_SIZE SZ_4K
#define ADI_SLAVE_OFFSET 0x8000
/* Timeout (ms) for the trylock of hardware spinlocks */
#define ADI_HWSPINLOCK_TIMEOUT 5000
/*
* ADI controller has 50 channels including 2 software channels
* and 48 hardware channels.
*/
#define ADI_HW_CHNS 50
#define ADI_FIFO_DRAIN_TIMEOUT 1000
#define ADI_READ_TIMEOUT 2000
#define REG_ADDR_LOW_MASK GENMASK(11, 0)
struct sprd_adi {
struct spi_controller *ctlr;
struct device *dev;
void __iomem *base;
struct hwspinlock *hwlock;
unsigned long slave_vbase;
unsigned long slave_pbase;
};
static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
{
if (paddr < sadi->slave_pbase || paddr >
(sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
dev_err(sadi->dev,
"slave physical address is incorrect, addr = 0x%x\n",
paddr);
return -EINVAL;
}
return 0;
}
static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
{
return (paddr - sadi->slave_pbase + sadi->slave_vbase);
}
static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
{
u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
u32 sts;
do {
sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
if (sts & BIT_FIFO_EMPTY)
break;
cpu_relax();
} while (--timeout);
if (timeout == 0) {
dev_err(sadi->dev, "drain write fifo timeout\n");
return -EBUSY;
}
return 0;
}
static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
{
return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
}
static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
{
int read_timeout = ADI_READ_TIMEOUT;
u32 val, rd_addr;
/*
* Set the physical register address need to read into RD_CMD register,
* then ADI controller will start to transfer automatically.
*/
writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
/*
* Wait read operation complete, the BIT_RD_CMD_BUSY will be set
* simultaneously when writing read command to register, and the
* BIT_RD_CMD_BUSY will be cleared after the read operation is
* completed.
*/
do {
val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
if (!(val & BIT_RD_CMD_BUSY))
break;
cpu_relax();
} while (--read_timeout);
if (read_timeout == 0) {
dev_err(sadi->dev, "ADI read timeout\n");
return -EBUSY;
}
/*
* The return value includes data and read register address, from bit 0
* to bit 15 are data, and from bit 16 to bit 30 are read register
* address. Then we can check the returned register address to validate
* data.
*/
rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
reg_paddr, val);
return -EIO;
}
*read_val = val & RD_VALUE_MASK;
return 0;
}
static int sprd_adi_write(struct sprd_adi *sadi, unsigned long reg, u32 val)
{
u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
int ret;
ret = sprd_adi_drain_fifo(sadi);
if (ret < 0)
return ret;
/*
* we should wait for write fifo is empty before writing data to PMIC
* registers.
*/
do {
if (!sprd_adi_fifo_is_full(sadi)) {
writel_relaxed(val, (void __iomem *)reg);
break;
}
cpu_relax();
} while (--timeout);
if (timeout == 0) {
dev_err(sadi->dev, "write fifo is full\n");
return -EBUSY;
}
return 0;
}
static int sprd_adi_transfer_one(struct spi_controller *ctlr,
struct spi_device *spi_dev,
struct spi_transfer *t)
{
struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
unsigned long flags, virt_reg;
u32 phy_reg, val;
int ret;
if (t->rx_buf) {
phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;
ret = sprd_adi_check_paddr(sadi, phy_reg);
if (ret)
return ret;
ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
ADI_HWSPINLOCK_TIMEOUT,
&flags);
if (ret) {
dev_err(sadi->dev, "get the hw lock failed\n");
return ret;
}
ret = sprd_adi_read(sadi, phy_reg, &val);
hwspin_unlock_irqrestore(sadi->hwlock, &flags);
if (ret)
return ret;
*(u32 *)t->rx_buf = val;
} else if (t->tx_buf) {
u32 *p = (u32 *)t->tx_buf;
/*
* Get the physical register address need to write and convert
* the physical address to virtual address. Since we need
* virtual register address to write.
*/
phy_reg = *p++ + sadi->slave_pbase;
ret = sprd_adi_check_paddr(sadi, phy_reg);
if (ret)
return ret;
virt_reg = sprd_adi_to_vaddr(sadi, phy_reg);
val = *p;
ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
ADI_HWSPINLOCK_TIMEOUT,
&flags);
if (ret) {
dev_err(sadi->dev, "get the hw lock failed\n");
return ret;
}
ret = sprd_adi_write(sadi, virt_reg, val);
hwspin_unlock_irqrestore(sadi->hwlock, &flags);
if (ret)
return ret;
} else {
dev_err(sadi->dev, "no buffer for transfer\n");
return -EINVAL;
}
return 0;
}
static void sprd_adi_hw_init(struct sprd_adi *sadi)
{
struct device_node *np = sadi->dev->of_node;
int i, size, chn_cnt;
const __be32 *list;
u32 tmp;
/* Address bits select default 12 bits */
writel_relaxed(0, sadi->base + REG_ADI_CTRL0);
/* Set all channels as default priority */
writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
/* Set clock auto gate mode */
tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
tmp &= ~BIT_CLK_ALL_ON;
writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
/* Set hardware channels setting */
list = of_get_property(np, "sprd,hw-channels", &size);
if (!list || !size) {
dev_info(sadi->dev, "no hw channels setting in node\n");
return;
}
chn_cnt = size / 8;
for (i = 0; i < chn_cnt; i++) {
u32 value;
u32 chn_id = be32_to_cpu(*list++);
u32 chn_config = be32_to_cpu(*list++);
/* Channel 0 and 1 are software channels */
if (chn_id < 2)
continue;
writel_relaxed(chn_config, sadi->base +
REG_ADI_CHN_ADDR(chn_id));
if (chn_id < 32)
|