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/*
* Microchip PIC32 SPI controller driver.
*
* Purna Chandra Mandal <purna.mandal@microchip.com>
* Copyright (c) 2016, Microchip Technology Inc.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/highmem.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
/* SPI controller registers */
struct pic32_spi_regs {
u32 ctrl;
u32 ctrl_clr;
u32 ctrl_set;
u32 ctrl_inv;
u32 status;
u32 status_clr;
u32 status_set;
u32 status_inv;
u32 buf;
u32 dontuse[3];
u32 baud;
u32 dontuse2[3];
u32 ctrl2;
u32 ctrl2_clr;
u32 ctrl2_set;
u32 ctrl2_inv;
};
/* Bit fields of SPI Control Register */
#define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
#define RX_FIFO_EMPTY 0
#define RX_FIFO_NOT_EMPTY 1 /* not empty */
#define RX_FIFO_HALF_FULL 2 /* full by half or more */
#define RX_FIFO_FULL 3 /* completely full */
#define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
#define TX_FIFO_ALL_EMPTY 0 /* completely empty */
#define TX_FIFO_EMPTY 1 /* empty */
#define TX_FIFO_HALF_EMPTY 2 /* empty by half or more */
#define TX_FIFO_NOT_FULL 3 /* atleast one empty */
#define CTRL_MSTEN BIT(5) /* enable master mode */
#define CTRL_CKP BIT(6) /* active low */
#define CTRL_CKE BIT(8) /* Tx on falling edge */
#define CTRL_SMP BIT(9) /* Rx at middle or end of tx */
#define CTRL_BPW_MASK 0x03 /* bits per word/sample */
#define CTRL_BPW_SHIFT 10
#define PIC32_BPW_8 0
#define PIC32_BPW_16 1
#define PIC32_BPW_32 2
#define CTRL_SIDL BIT(13) /* sleep when idle */
#define CTRL_ON BIT(15) /* enable macro */
#define CTRL_ENHBUF BIT(16) /* enable enhanced buffering */
#define CTRL_MCLKSEL BIT(23) /* select clock source */
#define CTRL_MSSEN BIT(28) /* macro driven /SS */
#define CTRL_FRMEN BIT(31) /* enable framing mode */
/* Bit fields of SPI Status Register */
#define STAT_RF_EMPTY BIT(5) /* RX Fifo empty */
#define STAT_RX_OV BIT(6) /* err, s/w needs to clear */
#define STAT_TX_UR BIT(8) /* UR in Framed SPI modes */
#define STAT_FRM_ERR BIT(12) /* Multiple Frame Sync pulse */
#define STAT_TF_LVL_MASK 0x1F
#define STAT_TF_LVL_SHIFT 16
#define STAT_RF_LVL_MASK 0x1F
#define STAT_RF_LVL_SHIFT 24
/* Bit fields of SPI Baud Register */
#define BAUD_MASK 0x1ff
/* Bit fields of SPI Control2 Register */
#define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */
#define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */
#define CTRL2_FRM_ERR_EN BIT(12) /* Enable frame err int */
/* Minimum DMA transfer size */
#define PIC32_DMA_LEN_MIN 64
struct pic32_spi {
dma_addr_t dma_base;
struct pic32_spi_regs __iomem *regs;
int fault_irq;
int rx_irq;
int tx_irq;
u32 fifo_n_byte; /* FIFO depth in bytes */
struct clk *clk;
struct spi_master *master;
/* Current controller setting */
u32 speed_hz; /* spi-clk rate */
u32 mode;
u32 bits_per_word;
u32 fifo_n_elm; /* FIFO depth in words */
#define PIC32F_DMA_PREP 0 /* DMA chnls configured */
unsigned long flags;
/* Current transfer state */
struct completion xfer_done;
/* PIO transfer specific */
const void *tx;
const void *tx_end;
const void *rx;
const void *rx_end;
int len;
void (*rx_fifo)(struct pic32_spi *);
void (*tx_fifo)(struct pic32_spi *);
};
static inline void pic32_spi_enable(struct pic32_spi *pic32s)
{
writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set);
}
static inline void pic32_spi_disable(struct pic32_spi *pic32s)
{
writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr);
/* avoid SPI registers read/write at immediate next CPU clock */
ndelay(20);
}
static void pic32_spi_set_clk_rate(struct pic32_spi *pic32s, u32 spi_ck)
{
u32 div;
/* div = (clk_in / 2 * spi_ck) - 1 */
div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1;
writel(div & BAUD_MASK, &pic32s->regs->baud);
}
static inline u32 pic32_rx_fifo_level(struct pic32_spi *pic32s)
{
u32 sr = readl(&pic32s->regs->status);
return (sr >> STAT_RF_LVL_SHIFT) & STAT_RF_LVL_MASK;
}
static inline u32 pic32_tx_fifo_level(struct pic32_spi *pic32s)
{
u32 sr = readl(&pic32s->regs->status);
return (sr >> STAT_TF_LVL_SHIFT) & STAT_TF_LVL_MASK;
}
/* Return the max entries we can fill into tx fifo */
static u32 pic32_tx_max(struct pic32_spi *pic32s, int n_bytes)
{
u32 tx_left, tx_room, rxtx_gap;
tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes;
tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s);
/*
* Another concern is about the tx/rx mismatch, we
* though to use (pic32s->fifo_n_byte - rxfl - txfl) as
* one maximum value for tx, but it doesn't cover the
* data which is out of tx/rx fifo and inside the
* shift registers. So a ctrl from sw point of
* view is taken.
*/
rxtx_gap = ((pic32s->rx_end - pic32s->rx) -
(pic32s->tx_end - pic32s->tx)) / n_bytes;
return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap));
}
/* Return the max entries we should read out of rx fifo */
static u32 pic32_rx_max(struct pic32_spi *pic32s, int n_bytes)
{
u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes;
return min_t(u32, rx_left, pic32_rx_fifo_level(pic32s));
}
#define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
static void pic32_spi_rx_##__name(struct pic32_spi *pic32s) \
{ \
__type v; \
u32 mx = pic32_rx_max(pic32s, sizeof(__type)); \
for (; mx; mx--) { \
v = read##__bwl(&pic32s->regs->buf); \
if (pic32s->rx_end - pic32s->len) \
*(__type *)(pic32s->rx) = v; \
pic32s->rx += sizeof(__type); \
} \
} \
\
static void pic32_spi_tx_##__name(struct pic32_spi *pic32s) \
{ \
__type v; \
u32 mx = pic32_tx_max(pic32s, sizeof(__type)); \
for (; mx ; mx--) { \
v = (__type)~0U; \
if (pic32s->tx_end - pic32s->len) \
v = *(__type *)(pic32s->tx); \
write##__bwl(v, &pic32s->regs->buf); \
pic32s->tx += sizeof(__type); \
} \
}
BUILD_SPI_FIFO_RW(byte, u8, b);
BUILD_SPI_FIFO_RW(word
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