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/*
* PIC32 Quad SPI controller driver.
*
* Purna Chandra Mandal <purna.mandal@microchip.com>
* Copyright (c) 2016, Microchip Technology Inc.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
/* SQI registers */
#define PESQI_XIP_CONF1_REG 0x00
#define PESQI_XIP_CONF2_REG 0x04
#define PESQI_CONF_REG 0x08
#define PESQI_CTRL_REG 0x0C
#define PESQI_CLK_CTRL_REG 0x10
#define PESQI_CMD_THRES_REG 0x14
#define PESQI_INT_THRES_REG 0x18
#define PESQI_INT_ENABLE_REG 0x1C
#define PESQI_INT_STAT_REG 0x20
#define PESQI_TX_DATA_REG 0x24
#define PESQI_RX_DATA_REG 0x28
#define PESQI_STAT1_REG 0x2C
#define PESQI_STAT2_REG 0x30
#define PESQI_BD_CTRL_REG 0x34
#define PESQI_BD_CUR_ADDR_REG 0x38
#define PESQI_BD_BASE_ADDR_REG 0x40
#define PESQI_BD_STAT_REG 0x44
#define PESQI_BD_POLL_CTRL_REG 0x48
#define PESQI_BD_TX_DMA_STAT_REG 0x4C
#define PESQI_BD_RX_DMA_STAT_REG 0x50
#define PESQI_THRES_REG 0x54
#define PESQI_INT_SIGEN_REG 0x58
/* PESQI_CONF_REG fields */
#define PESQI_MODE 0x7
#define PESQI_MODE_BOOT 0
#define PESQI_MODE_PIO 1
#define PESQI_MODE_DMA 2
#define PESQI_MODE_XIP 3
#define PESQI_MODE_SHIFT 0
#define PESQI_CPHA BIT(3)
#define PESQI_CPOL BIT(4)
#define PESQI_LSBF BIT(5)
#define PESQI_RXLATCH BIT(7)
#define PESQI_SERMODE BIT(8)
#define PESQI_WP_EN BIT(9)
#define PESQI_HOLD_EN BIT(10)
#define PESQI_BURST_EN BIT(12)
#define PESQI_CS_CTRL_HW BIT(15)
#define PESQI_SOFT_RESET BIT(16)
#define PESQI_LANES_SHIFT 20
#define PESQI_SINGLE_LANE 0
#define PESQI_DUAL_LANE 1
#define PESQI_QUAD_LANE 2
#define PESQI_CSEN_SHIFT 24
#define PESQI_EN BIT(23)
/* PESQI_CLK_CTRL_REG fields */
#define PESQI_CLK_EN BIT(0)
#define PESQI_CLK_STABLE BIT(1)
#define PESQI_CLKDIV_SHIFT 8
#define PESQI_CLKDIV 0xff
/* PESQI_INT_THR/CMD_THR_REG */
#define PESQI_TXTHR_MASK 0x1f
#define PESQI_TXTHR_SHIFT 8
#define PESQI_RXTHR_MASK 0x1f
#define PESQI_RXTHR_SHIFT 0
/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */
#define PESQI_TXEMPTY BIT(0)
#define PESQI_TXFULL BIT(1)
#define PESQI_TXTHR BIT(2)
#define PESQI_RXEMPTY BIT(3)
#define PESQI_RXFULL BIT(4)
#define PESQI_RXTHR BIT(5)
#define PESQI_BDDONE BIT(9) /* BD processing complete */
#define PESQI_PKTCOMP BIT(10) /* packet processing complete */
#define PESQI_DMAERR BIT(11) /* error */
/* PESQI_BD_CTRL_REG */
#define PESQI_DMA_EN BIT(0) /* enable DMA engine */
#define PESQI_POLL_EN BIT(1) /* enable polling */
#define PESQI_BDP_START BIT(2) /* start BD processor */
/* PESQI controller buffer descriptor */
struct buf_desc {
u32 bd_ctrl; /* control */
u32 bd_status; /* reserved */
u32 bd_addr; /* DMA buffer addr */
u32 bd_nextp; /* next item in chain */
};
/* bd_ctrl */
#define BD_BUFLEN 0x1ff
#define BD_CBD_INT_EN BIT(16) /* Current BD is processed */
#define BD_PKT_INT_EN BIT(17) /* All BDs of PKT processed */
#define BD_LIFM BIT(18) /* last data of pkt */
#define BD_LAST BIT(19) /* end of list */
#define BD_DATA_RECV BIT(20) /* receive data */
#define BD_DDR BIT(21) /* DDR mode */
#define BD_DUAL BIT(22) /* Dual SPI */
#define BD_QUAD BIT(23) /* Quad SPI */
#define BD_LSBF BIT(25) /* LSB First */
#define BD_STAT_CHECK BIT(27) /* Status poll */
#define BD_DEVSEL_SHIFT 28 /* CS */
#define BD_CS_DEASSERT BIT(30) /* de-assert CS after current BD */
#define BD_EN BIT(31) /* BD owned by H/W */
/**
* struct ring_desc - Representation of SQI ring descriptor
* @list: list element to add to free or used list.
* @bd: PESQI controller buffer descriptor
* @bd_dma: DMA address of PESQI controller buffer descriptor
* @xfer_len: transfer length
*/
struct ring_desc {
struct list_head list;
struct buf_desc *bd;
dma_addr_t bd_dma;
u32 xfer_len;
};
/* Global constants */
#define PESQI_BD_BUF_LEN_MAX 256
#define PESQI_BD_COUNT 256 /* max 64KB data per spi message */
struct pic32_sqi {
void __iomem *regs;
struct clk *sys_clk;
struct clk *base_clk; /* drives spi clock */
struct spi_master *master;
int irq;
struct completion xfer_done;
struct ring_desc *ring;
void *bd;
dma_addr_t bd_dma;
struct list_head bd_list_free; /* free */
struct list_head bd_list_used; /* allocated */
struct spi_device *cur_spi;
u32 cur_speed;
u8 cur_mode;
};
static inline void pic32_setbits(void __iomem *reg, u32 set)
{
writel(readl(reg) | set, reg);
}
static inline void pic32_clrbits(void __iomem *reg, u32 clr)
{
writel(readl(reg) & ~clr, reg);
}
static int pic32_sqi_set_clk_rate(struct pic32_sqi *sqi, u32 sck)
{
u32 val, div;
/* div = base_clk / (2 * spi_clk) */
div = clk_get_rate(sqi->base_clk) / (2 * sck);
div &= PESQI_CLKDIV;
val = readl(sqi->regs + PESQI_CLK_CTRL_REG);
/* apply new divider */
val &= ~(PESQI_CLK_STABLE | (PESQI_CLKDIV << PESQI_CLKDIV_SHIFT));
val |= div << PESQI_CLKDIV_SHIFT;
writel(val, sqi->regs + PESQI_CLK_CTRL_REG);
/* wait for stability */
return readl_poll_timeout(sqi->regs + PESQI_CLK_CTRL_REG, val,
val & PESQI_CLK_STABLE, 1, 5000);
}
static inline void pic32_sqi_enable_int(struct pic32_sqi *sqi)
{
u32 mask = PESQI_DMAERR | PESQI_BDDONE | PESQI_PKTCOMP;
writel(mask, sqi->regs + PESQI_INT_ENABLE_REG);
/* INT_SIGEN works as interrupt-gate to INTR line */
writel(mask, sqi->regs + PESQI_INT_SIGEN_REG);
}
static inline void pic32_sqi_disable_int(struct pic32_sqi *sqi)
{
writel(0, sqi->regs + PESQI_INT_ENABLE_REG);
writel(0, sqi->regs + PESQI_INT_SIGEN_REG);
}
static irqreturn_t pic32_sqi_isr(int irq, void *dev_id)
{
struct pic32_sqi *sqi = dev_id;
u32 enable, status;
enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
status = readl(sqi->regs + PESQI_INT_STAT_REG);
/* check spurious interrupt */
if (!status)
return IRQ_NONE;
if (status & PESQI_DMAERR) {
enable = 0;
goto irq_done;
}
if (status & PESQI_TXTHR)
enable &= ~(PESQI_TXTHR | PESQI_TXFULL | PESQI_TXEMPTY);
if (status & PESQI_RXTHR)
enable &= ~(PESQI_RXTHR | PESQI_RXFULL | PESQI_RXEMPTY);
if (status & PESQI_BDDONE)
enable &= ~PESQI_BDDONE;
/* packet processing completed */
if (status & PESQI_PKTCOMP) {
/* mask all interrupts */
enable = 0;
/* complete trasaction */
complete(&sqi->xfer_done);
}
irq_done:
/* interrupts are sticky, so mask when handled */
writel(enable, sqi->regs + PESQI_INT_ENABLE_REG);
return IRQ_HANDLED;
}
static struct ring_desc *ring_desc_get(struct pic32_sqi *sqi)
{
struct ring_desc *rdesc;
if (list_empty(&sqi->bd_list_free))
return NULL;
rdesc = list_first_entry(&sqi->bd_list_free, struct ring_desc, list);
list_move_tail(&rdesc->list, &sqi->bd_list_used);
return rdesc;
}
static void ring_desc_put(struct pic32_sqi *sqi, struct ring_desc *rdesc)
{
list_move(&rdesc->list, &sqi->bd_list_free);
}
static int pic32_sqi_one_transfer(struct pic32_sqi *sqi,
struct spi_message *mesg,
struct spi_transfer *
|