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|
/*
* Broadcom BCM63XX High Speed SPI Controller driver
*
* Copyright 2000-2010 Broadcom Corporation
* Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/mutex.h>
#include <linux/of.h>
#define HSSPI_GLOBAL_CTRL_REG 0x0
#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
#define HSSPI_INT_STATUS_REG 0x8
#define HSSPI_INT_STATUS_MASKED_REG 0xc
#define HSSPI_INT_MASK_REG 0x10
#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
#define HSSPI_INT_CLEAR_ALL 0xff001f1f
#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
#define PINGPONG_CMD_COMMAND_MASK 0xf
#define PINGPONG_COMMAND_NOOP 0
#define PINGPONG_COMMAND_START_NOW 1
#define PINGPONG_COMMAND_START_TRIGGER 2
#define PINGPONG_COMMAND_HALT 3
#define PINGPONG_COMMAND_FLUSH 4
#define PINGPONG_CMD_PROFILE_SHIFT 8
#define PINGPONG_CMD_SS_SHIFT 12
#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
#define SIGNAL_CTRL_LATCH_RISING BIT(12)
#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
#define MODE_CTRL_MODE_3WIRE BIT(20)
#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
#define HSSPI_OP_MULTIBIT BIT(11)
#define HSSPI_OP_CODE_SHIFT 13
#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
#define HSSPI_BUFFER_LEN 512
#define HSSPI_OPCODE_LEN 2
#define HSSPI_MAX_PREPEND_LEN 15
#define HSSPI_MAX_SYNC_CLOCK 30000000
#define HSSPI_SPI_MAX_CS 8
#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
struct bcm63xx_hsspi {
struct completion done;
struct mutex bus_mutex;
struct platform_device *pdev;
struct clk *clk;
void __iomem *regs;
u8 __iomem *fifo;
u32 speed_hz;
u8 cs_polarity;
};
static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
bool active)
{
u32 reg;
mutex_lock(&bs->bus_mutex);
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
reg &= ~BIT(cs);
if (active == !(bs->cs_polarity & BIT(cs)))
reg |= BIT(cs);
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
mutex_unlock(&bs->bus_mutex);
}
static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
struct spi_device *spi, int hz)
{
unsigned int profile = spi->chip_select;
u32 reg;
reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
if (hz > HSSPI_MAX_SYNC_CLOCK)
reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
else
reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
mutex_lock(&bs->bus_mutex);
/* setup clock polarity */
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
reg &= ~GLOBAL_CTRL_CLK_POLARITY;
if (spi->mode & SPI_CPOL)
reg |= GLOBAL_CTRL_CLK_POLARITY;
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
mutex_unlock(&bs->bus_mutex);
}
static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
{
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
unsigned int chip_select = spi->chip_select;
u16 opcode = 0;
int pending = t->len;
int step_size = HSSPI_BUFFER_LEN;
const u8 *tx = t->tx_buf;
u8 *rx = t->rx_buf;
bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
if (tx && rx)
opcode = HSSPI_OP_READ_WRITE;
else if (tx)
opcode = HSSPI_OP_WRITE;
else if (rx)
opcode = HSSPI_OP_READ;
if (opcode != HSSPI_OP_READ)
step_size -= HSSPI_OPCODE_LEN;
if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
(opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
opcode |= HSSPI_OP_MULTIBIT;
__raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
while (pending > 0) {
int curr_step = min_t(int, step_size, pending);
reinit_completion(&bs->done);
if (tx) {
memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
tx += curr_step;
}
__raw_writew(opcode | curr_step, bs->fifo);
/* enable interrupt */
__raw_writel(HSSPI_PINGx_CMD_DONE(0),
bs->regs + HSSPI_INT_MASK_REG);
/* start the transfer */
__raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
chip_select << PINGPONG_CMD_PROFILE_SHIFT |
PINGPONG_COMMAND_START_NOW,
bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
dev_err(&bs->pdev->dev, "transfer timed out!\n");
return -ETIMEDOUT;
}
if (rx) {
memcpy_fromio(rx, bs->fifo, curr_step);
rx += curr_step;
}
pending -= curr_step;
}
return 0;
}
static int bcm63xx_hsspi_setup(struct spi_device *spi)
{
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
u32 reg;
reg = __raw_readl(bs->regs +
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
if (spi->mode & SPI_CPHA)
reg |= SIGNAL_CTRL_LAUNCH_RISING;
else
reg |= SIGNAL_CTRL_LATCH_RISING;
__raw_writel(reg, bs->regs +
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
mutex_lock(&bs->bus_mutex);
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
/* only change actual polarities if there is no transfer */
if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
if (spi->mode & SPI_CS_HIGH)
reg |= BIT(spi->chip_select);
else
reg &= ~BIT(spi->chip_select);
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
}
if (spi->mode & SPI_CS_HIGH)
bs->cs_polarity |= BIT(spi->chip_select);
else
bs->cs_polarity &= ~BIT(spi->chip_select);
mutex_unlock(&bs->bus_mutex);
return 0;
}
static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
struct spi_message *msg)
{
struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
struct spi_transfer *t;
struct spi_device *spi = msg->spi;
int status = -EINVAL;
int dummy_cs;
u32 reg;
/* This controller does not support keeping CS active during idle.
* To work around this, we use the following ugly hack:
*
* a. Invert the target chip select's polarity so it will be active.
* b. Select
|