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|
// SPDX-License-Identifier: GPL-2.0+
/*
* rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
* I2C RTC / Alarm chip
*
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
*
* Detailed datasheet of the chip is available here:
*
* http://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
*
* This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
*
*/
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/interrupt.h>
#define DRV_NAME "rtc-ab-b5ze-s3"
/* Control section */
#define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */
#define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
#define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
#define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
#define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */
#define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */
#define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
#define ABB5ZES3_REG_CTRL1_CAP BIT(7)
#define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */
#define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
#define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */
#define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */
#define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */
#define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */
#define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */
#define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */
#define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */
#define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */
#define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */
#define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */
#define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */
#define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */
#define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */
#define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */
#define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */
#define ABB5ZES3_CTRL_SEC_LEN 3
/* RTC section */
#define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */
#define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */
#define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */
#define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */
#define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */
#define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */
#define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */
#define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */
#define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */
#define ABB5ZES3_RTC_SEC_LEN 7
/* Alarm section (enable bits are all active low) */
#define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
#define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */
#define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
#define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */
#define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
#define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */
#define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
#define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */
#define ABB5ZES3_ALRM_SEC_LEN 4
/* Frequency offset section */
#define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */
#define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */
/* CLOCKOUT section */
#define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */
#define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */
#define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */
#define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
#define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */
#define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */
#define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */
#define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */
#define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */
/* Timer A Section */
#define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */
#define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */
#define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */
#define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */
#define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */
#define ABB5ZES3_TIMA_SEC_LEN 2
/* Timer B Section */
#define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */
#define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
#define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
#define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
#define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
#define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
#define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
#define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */
#define ABB5ZES3_TIMB_SEC_LEN 2
#define ABB5ZES3_MEM_MAP_LEN 0x14
struct abb5zes3_rtc_data {
struct rtc_device *rtc;
struct regmap *regmap;
int irq;
bool battery_low;
bool timer_alarm; /* current alarm is via timer A */
};
/*
* Try and match register bits w/ fixed null values to see whether we
* are dealing with an ABB5ZES3.
*/
static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
{
u8 regs[ABB5ZES3_MEM_MAP_LEN];
static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
0x80, 0xc0, 0xc0, 0xf8,
0xe0, 0x00, 0x00, 0x40,
0x40, 0x78, 0x00, 0x00,
0xf8, 0x00, 0x88, 0x00 };
int ret, i;
ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
if (ret)
return ret;
for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
if (regs[i] & mask[i]) /* check if bits are cleared */
return -ENODEV;
}
return 0;
}
/* Clear alarm status bit. */
static int _abb5zes3_rtc_clear_alarm(struct device *dev)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
ABB5ZES3_REG_CTRL2_AF, 0);
if (ret)
dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
return ret;
}
/* Enable or disable alarm (i.e. alarm interrupt generation) */
static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
ABB5ZES3_REG_CTRL1_AIE,
enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
if (ret)
dev_err(dev, "%s: writing alarm INT failed (%d)\n",
__func__, ret);
return ret;
}
/* Enable or disable timer (watchdog timer A interrupt generation) */
static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
ABB5ZES3_REG_CTRL2_WTAIE,
enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
if (ret)
dev_err(dev, "%s: writing timer INT failed (%d)\n",
__func__, ret);
return ret;
}
/*
* Note: we only read, so regmap inner lock protection is sufficient, i.e.
* we do not need driver's main lock protection.
*/
static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
|