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|
/*
* Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
*
* Copyright (C) 2016 Linaro Ltd
* Copyright (C) 2014 Sony Mobile Communications AB
* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/qcom_scm.h>
#include <linux/regulator/consumer.h>
#include <linux/remoteproc.h>
#include <linux/soc/qcom/mdt_loader.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>
#include <linux/rpmsg/qcom_smd.h>
#include "qcom_common.h"
#include "remoteproc_internal.h"
#include "qcom_wcnss.h"
#define WCNSS_CRASH_REASON_SMEM 422
#define WCNSS_FIRMWARE_NAME "wcnss.mdt"
#define WCNSS_PAS_ID 6
#define WCNSS_SPARE_NVBIN_DLND BIT(25)
#define WCNSS_PMU_IRIS_XO_CFG BIT(3)
#define WCNSS_PMU_IRIS_XO_EN BIT(4)
#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
#define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
#define WCNSS_PMU_IRIS_RESET BIT(7)
#define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
#define WCNSS_PMU_IRIS_XO_READ BIT(9)
#define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
#define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
#define WCNSS_PMU_XO_MODE_19p2 0
#define WCNSS_PMU_XO_MODE_48 3
struct wcnss_data {
size_t pmu_offset;
size_t spare_offset;
const struct wcnss_vreg_info *vregs;
size_t num_vregs;
};
struct qcom_wcnss {
struct device *dev;
struct rproc *rproc;
void __iomem *pmu_cfg;
void __iomem *spare_out;
bool use_48mhz_xo;
int wdog_irq;
int fatal_irq;
int ready_irq;
int handover_irq;
int stop_ack_irq;
struct qcom_smem_state *state;
unsigned stop_bit;
struct mutex iris_lock;
struct qcom_iris *iris;
struct regulator_bulk_data *vregs;
size_t num_vregs;
struct completion start_done;
struct completion stop_done;
phys_addr_t mem_phys;
phys_addr_t mem_reloc;
void *mem_region;
size_t mem_size;
struct qcom_rproc_subdev smd_subdev;
};
static const struct wcnss_data riva_data = {
.pmu_offset = 0x28,
.spare_offset = 0xb4,
.vregs = (struct wcnss_vreg_info[]) {
{ "vddmx", 1050000, 1150000, 0 },
{ "vddcx", 1050000, 1150000, 0 },
{ "vddpx", 1800000, 1800000, 0 },
},
.num_vregs = 3,
};
static const struct wcnss_data pronto_v1_data = {
.pmu_offset = 0x1004,
.spare_offset = 0x1088,
.vregs = (struct wcnss_vreg_info[]) {
{ "vddmx", 950000, 1150000, 0 },
{ "vddcx", .super_turbo = true},
{ "vddpx", 1800000, 1800000, 0 },
},
.num_vregs = 3,
};
static const struct wcnss_data pronto_v2_data = {
.pmu_offset = 0x1004,
.spare_offset = 0x1088,
.vregs = (struct wcnss_vreg_info[]) {
{ "vddmx", 1287500, 1287500, 0 },
{ "vddcx", .super_turbo = true },
{ "vddpx", 1800000, 1800000, 0 },
},
.num_vregs = 3,
};
void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
struct qcom_iris *iris,
bool use_48mhz_xo)
{
mutex_lock(&wcnss->iris_lock);
wcnss->iris = iris;
wcnss->use_48mhz_xo = use_48mhz_xo;
mutex_unlock(&wcnss->iris_lock);
}
static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
{
struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
wcnss->mem_region, wcnss->mem_phys, wcnss->mem_size);
}
static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
{
u32 val;
/* Indicate NV download capability */
val = readl(wcnss->spare_out);
val |= WCNSS_SPARE_NVBIN_DLND;
writel(val, wcnss->spare_out);
}
static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
{
u32 val;
/* Clear PMU cfg register */
writel(0, wcnss->pmu_cfg);
val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
writel(val, wcnss->pmu_cfg);
/* Clear XO_MODE */
val &= ~WCNSS_PMU_XO_MODE_MASK;
if (wcnss->use_48mhz_xo)
val |= WCNSS_PMU_XO_MODE_48 << 1;
else
val |= WCNSS_PMU_XO_MODE_19p2 << 1;
writel(val, wcnss->pmu_cfg);
/* Reset IRIS */
val |= WCNSS_PMU_IRIS_RESET;
writel(val, wcnss->pmu_cfg);
/* Wait for PMU.iris_reg_reset_sts */
while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
cpu_relax();
/* Clear IRIS reset */
val &= ~WCNSS_PMU_IRIS_RESET;
writel(val, wcnss->pmu_cfg);
/* Start IRIS XO configuration */
val |= WCNSS_PMU_IRIS_XO_CFG;
writel(val, wcnss->pmu_cfg);
/* Wait for XO configuration to finish */
while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
cpu_relax();
/* Stop IRIS XO configuration */
val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
val &= ~WCNSS_PMU_IRIS_XO_CFG;
writel(val, wcnss->pmu_cfg);
/* Add some delay for XO to settle */
msleep(20);
}
static int wcnss_start(struct rproc *rproc)
{
struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
int ret;
mutex_lock(&wcnss->iris_lock);
if (!wcnss->iris) {
dev_err(wcnss->dev, "no iris registered\n");
ret = -EINVAL;
goto release_iris_lock;
}
ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
if (ret)
goto release_iris_lock;
ret = qcom_iris_enable(wcnss->iris);
if (ret)
goto disable_regulators;
wcnss_indicate_nv_download(wcnss);
wcnss_configure_iris(wcnss);
ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
if (ret) {
dev_err(wcnss->dev,
"failed to authenticate image and release reset\n");
goto disable_iris;
}
ret = wait_for_completion_timeout(&wcnss->start_done,
msecs_to_jiffies(5000));
if (wcnss->ready_irq > 0 && ret == 0) {
/* We have a ready_irq, but it didn't fire in time. */
dev_err(wcnss->dev, "start timed out\n");
qcom_scm_pas_shutdown(WCNSS_PAS_ID);
ret = -ETIMEDOUT;
goto
|