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/*
* Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins
*
* Copyright (c) 2013, Imagination Technologies Ltd.
*
* Derived from Tegra code:
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code:
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010 NVIDIA Corporation
* Copyright (C) 2009-2011 ST-Ericsson AB
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
/*
* The registers may be shared with other threads/cores, so we need to use the
* metag global lock2 for atomicity.
*/
#include <asm/global_lock.h>
#include "core.h"
#include "pinconf.h"
/* Register offsets from bank base address */
#define REG_GPIO_CONTROL0 0x00
#define REG_GPIO_CONTROL2 0x08
/* Register field information */
#define REG_GPIO_CONTROL2_PU_PD_S 16
#define REG_GPIO_CONTROL2_PDC_POS_S 4
#define REG_GPIO_CONTROL2_PDC_DR_S 2
#define REG_GPIO_CONTROL2_PDC_SR_S 1
#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0
/* PU_PD field values */
#define REG_PU_PD_TRISTATE 0
#define REG_PU_PD_UP 1
#define REG_PU_PD_DOWN 2
#define REG_PU_PD_REPEATER 3
/* DR field values */
#define REG_DR_2mA 0
#define REG_DR_4mA 1
#define REG_DR_8mA 2
#define REG_DR_12mA 3
/**
* struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function
* @name: The name of the function, exported to pinctrl core.
* @groups: An array of pin groups that may select this function.
* @ngroups: The number of entries in @groups.
*/
struct tz1090_pdc_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
};
/**
* struct tz1090_pdc_pingroup - TZ1090 PDC pin group
* @name: Name of pin group.
* @pins: Array of pin numbers in this pin group.
* @npins: Number of pins in this pin group.
* @func: Function enabled by the mux.
* @reg: Mux register offset.
* @bit: Mux register bit.
* @drv: Drive control supported, otherwise it's a mux.
* This means Schmitt, Slew, and Drive strength.
*
* A representation of a group of pins (possibly just one pin) in the TZ1090
* PDC pin controller. Each group allows some parameter or parameters to be
* configured. The most common is mux function selection.
*/
struct tz1090_pdc_pingroup {
const char *name;
const unsigned int *pins;
unsigned int npins;
int func;
u16 reg;
u8 bit;
bool drv;
};
/*
* All PDC pins can be GPIOs. Define these first to match how the GPIO driver
* names/numbers its pins.
*/
enum tz1090_pdc_pin {
TZ1090_PDC_PIN_GPIO0,
TZ1090_PDC_PIN_GPIO1,
TZ1090_PDC_PIN_SYS_WAKE0,
TZ1090_PDC_PIN_SYS_WAKE1,
TZ1090_PDC_PIN_SYS_WAKE2,
TZ1090_PDC_PIN_IR_DATA,
TZ1090_PDC_PIN_EXT_POWER,
};
/* Pin names */
static const struct pinctrl_pin_desc tz1090_pdc_pins[] = {
/* PDC GPIOs */
PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"),
PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"),
PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"),
PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"),
PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"),
PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"),
PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"),
};
/* Pin group pins */
static const unsigned int gpio0_pins[] = {
TZ1090_PDC_PIN_GPIO0,
};
static const unsigned int gpio1_pins[] = {
TZ1090_PDC_PIN_GPIO1,
};
static const unsigned int pdc_pins[] = {
TZ1090_PDC_PIN_GPIO0,
TZ1090_PDC_PIN_GPIO1,
TZ1090_PDC_PIN_SYS_WAKE0,
TZ1090_PDC_PIN_SYS_WAKE1,
TZ1090_PDC_PIN_SYS_WAKE2,
TZ1090_PDC_PIN_IR_DATA,
TZ1090_PDC_PIN_EXT_POWER,
};
/* Mux functions */
enum tz1090_pdc_mux {
/* PDC_GPIO0 mux */
TZ1090_PDC_MUX_IR_MOD_STABLE_OUT,
/* PDC_GPIO1 mux */
TZ1090_PDC_MUX_IR_MOD_POWER_OUT,
};
/* Pin groups a function can be muxed to */
static const char * const gpio0_groups[] = {
"gpio0",
};
static const char * const gpio1_groups[] = {
"gpio1",
};
#define FUNCTION(mux, fname, group) \
[(TZ1090_PDC_MUX_ ## mux)] = { \
.name = #fname, \
.groups = group##_groups, \
.ngroups = ARRAY_SIZE(group##_groups), \
}
/* Must correlate with enum tz1090_pdc_mux */
static const struct tz1090_pdc_function tz1090_pdc_functions[] = {
/* MUX fn pingroups */
FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0),
FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1),
};
/**
* MUX_PG() - Initialise a pin group with mux control
* @pg_name: Pin group name (stringified, _pins appended to get pins array)
* @f0: Function 0 (TZ1090_PDC_MUX_ is prepended)
* @mux_r: Mux register (REG_PINCTRL_ is prepended)
* @mux_b: Bit number in register of mux field
*/
#define MUX_PG(pg_name, f0, mux_r, mux_b) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.func = TZ1090_PDC_MUX_ ## f0, \
.reg = (REG_ ## mux_r), \
.bit = (mux_b), \
}
/**
* DRV_PG() - Initialise a pin group with drive control
* @pg_name: Pin group name (stringified, _pins appended to get pins array)
*/
#define DRV_PG(pg_name) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.drv = true, \
}
static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = {
/* Muxing pin groups */
/* pg_name, f0, mux register, mux bit */
MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7),
MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6),
/* Drive pin groups */
/* pg_name */
DRV_PG(pdc),
};
/**
* struct tz1090_pdc_pmx - Private pinctrl data
* @dev: Platform device
* @pctl: Pin control device
* @regs: Register region
* @lock: Lock protecting coherency of mux_en and gpio_en
* @mux_en: Muxes that have been enabled
* @gpio_en: Muxable GPIOs that have been enabled
*/
struct tz1090_pdc_pmx {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *regs;
spinlock_t lock;
u32 mux_en;
u32 gpio_en;
};
static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg)
{
return ioread32(pmx->regs + reg);
}
static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg)
{
iowrite32(val, pmx->regs + reg);
}
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