/*
* Driver for the Axis ARTPEC-6 pin controller
*
* Author: Chris Paterson <chris.paterson@linux.pieboy.co.uk>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
#define ARTPEC6_MAX_MUXABLE 35 /* Last pin with muxable function */
/* Pinmux control register bit definitions */
#define ARTPEC6_PINMUX_UDC0_MASK 0x00000001
#define ARTPEC6_PINMUX_UDC0_SHIFT 0
#define ARTPEC6_PINMUX_UDC1_MASK 0x00000002
#define ARTPEC6_PINMUX_UDC1_SHIFT 1
#define ARTPEC6_PINMUX_DRV_MASK 0x00000060
#define ARTPEC6_PINMUX_DRV_SHIFT 5
#define ARTPEC6_PINMUX_SEL_MASK 0x00003000
#define ARTPEC6_PINMUX_SEL_SHIFT 12
/* Pinmux configurations */
#define ARTPEC6_CONFIG_0 0
#define ARTPEC6_CONFIG_1 1
#define ARTPEC6_CONFIG_2 2
#define ARTPEC6_CONFIG_3 3
/* Pin drive strength options */
#define ARTPEC6_DRIVE_4mA 4
#define ARTPEC6_DRIVE_4mA_SET 0
#define ARTPEC6_DRIVE_6mA 6
#define ARTPEC6_DRIVE_6mA_SET 1
#define ARTPEC6_DRIVE_8mA 8
#define ARTPEC6_DRIVE_8mA_SET 2
#define ARTPEC6_DRIVE_9mA 9
#define ARTPEC6_DRIVE_9mA_SET 3
struct artpec6_pmx {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
struct pinctrl_pin_desc *pins;
unsigned int num_pins;
const struct artpec6_pin_group *pin_groups;
unsigned int num_pin_groups;
const struct artpec6_pmx_func *functions;
unsigned int num_functions;
};
struct artpec6_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int num_pins;
unsigned char config;
};
struct artpec6_pmx_func {
const char *name;
const char * const *groups;
const unsigned int num_groups;
};
/* pins */
static struct pinctrl_pin_desc artpec6_pins[] = {
PINCTRL_PIN(0, "GPIO0"),
PINCTRL_PIN(1, "GPIO1"),
PINCTRL_PIN(2, "GPIO2"),
PINCTRL_PIN(3, "GPIO3"),
PINCTRL_PIN(4, "GPIO4"),
PINCTRL_PIN(5, "GPIO5"),
PINCTRL_PIN(6, "GPIO6"),
PINCTRL_PIN(7, "GPIO7"),
PINCTRL_PIN(8, "GPIO8"),
PINCTRL_PIN(9, "GPIO9"),
PINCTRL_PIN(10, "GPIO10"),
PINCTRL_PIN(11, "GPIO11"),
PINCTRL_PIN(12, "GPIO12"),
PINCTRL_PIN(13, "GPIO13"),
PINCTRL_PIN(14, "GPIO14"),
PINCTRL_PIN(15, "GPIO15"),
PINCTRL_PIN(16, "GPIO16"),
PINCTRL_PIN(17, "GPIO17"),
PINCTRL_PIN(18, "GPIO18"),
PINCTRL_PIN(19, "GPIO19"),
PINCTRL_PIN(20, "GPIO20"),
PINCTRL_PIN(21, "GPIO21"),
PINCTRL_PIN(22, "GPIO22"),
PINCTRL_PIN(23, "GPIO23"),
PINCTRL_PIN(24, "GPIO24"),
PINCTRL_PIN(25, "GPIO25"),
PINCTRL_PIN(26, "GPIO26"),
PINCTRL_PIN(27, "GPIO27"),
PINCTRL_PIN(28, "GPIO28"),
PINCTRL_PIN(29, "GPIO29"),
PINCTRL_PIN(30, "GPIO30"),
PINCTRL_PIN(31, "GPIO31"),
PINCTRL_PIN(32, "UART3_TXD"),
PINCTRL_PIN(33, "UART3_RXD"),
PINCTRL_PIN(34, "UART3_RTS"),
PINCTRL_PIN(35, "UART3_CTS"),
PINCTRL_PIN(36, "NF_ALE"),
PINCTRL_PIN(37, "NF_CE0_N"),
PINCTRL_PIN(38, "NF_CE1_N"),
PINCTRL_PIN(39, "NF_CLE"),
PINCTRL_PIN(40, "NF_RE_N"),
PINCTRL_PIN(41, "NF_WE_N"),
PINCTRL_PIN(42, "NF_WP0_N"),
PINCTRL_PIN(43, "NF_WP1_N"),
PINCTRL_PIN(44, "NF_IO0"),
PINCTRL_PIN(45, "NF_IO1"),
PINCTRL_PIN(46, "NF_IO2"),
PINCTRL_PIN(47, "NF_IO3"),
PINCTRL_PIN(48, "NF_IO4"),
PINCTRL_PIN(49, "NF_IO5"),
PINCTRL_PIN(50, "NF_IO6"),
PINCTRL_PIN(51, "NF_IO7"),
PINCTRL_PIN(52, "NF_RB0_N"),
PINCTRL_PIN(53, "SDIO0_CLK"),
PINCTRL_PIN(54, "SDIO0_CMD"),
PINCTRL_PIN(55, "SDIO0_DAT0"),
PINCTRL_PIN(56, "SDIO0_DAT1"),
PINCTRL_PIN(57, "SDIO0_DAT2"),
PINCTRL_PIN(58, "SDIO0_DAT3"),
PINCTRL_PIN(59, "SDI0_CD"),
PINCTRL_PIN(60, "SDI0_WP"),
PINCTRL_PIN(61, "SDIO1_CLK"),
PINCTRL_PIN(62, "SDIO1_CMD"),
PINCTRL_PIN(63, "SDIO1_DAT0"),
PINCTRL_PIN(64, "SDIO1_DAT1"),
PINCTRL_PIN(65, "SDIO1_DAT2"),
PINCTRL_PIN(66, "SDIO1_DAT3"),
PINCTRL_PIN(67, "SDIO1_CD"),
PINCTRL