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/**
* APM X-Gene PCIe Driver
*
* Copyright (c) 2014 Applied Micro Circuits Corporation.
*
* Author: Tanmay Inamdar <tinamdar@apm.com>.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/memblock.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/pci-ecam.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#define PCIECORE_CTLANDSTATUS 0x50
#define PIM1_1L 0x80
#define IBAR2 0x98
#define IR2MSK 0x9c
#define PIM2_1L 0xa0
#define IBAR3L 0xb4
#define IR3MSKL 0xbc
#define PIM3_1L 0xc4
#define OMR1BARL 0x100
#define OMR2BARL 0x118
#define OMR3BARL 0x130
#define CFGBARL 0x154
#define CFGBARH 0x158
#define CFGCTL 0x15c
#define RTDID 0x160
#define BRIDGE_CFG_0 0x2000
#define BRIDGE_CFG_4 0x2010
#define BRIDGE_STATUS_0 0x2600
#define LINK_UP_MASK 0x00000100
#define AXI_EP_CFG_ACCESS 0x10000
#define EN_COHERENCY 0xF0000000
#define EN_REG 0x00000001
#define OB_LO_IO 0x00000002
#define XGENE_PCIE_VENDORID 0x10E8
#define XGENE_PCIE_DEVICEID 0xE004
#define SZ_1T (SZ_1G*1024ULL)
#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
#define XGENE_V1_PCI_EXP_CAP 0x40
/* PCIe IP version */
#define XGENE_PCIE_IP_VER_UNKN 0
#define XGENE_PCIE_IP_VER_1 1
#define XGENE_PCIE_IP_VER_2 2
#if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
struct xgene_pcie_port {
struct device_node *node;
struct device *dev;
struct clk *clk;
void __iomem *csr_base;
void __iomem *cfg_base;
unsigned long cfg_addr;
bool link_up;
u32 version;
};
static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
{
return readl(port->csr_base + reg);
}
static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
{
writel(val, port->csr_base + reg);
}
static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
{
return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
}
static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
{
struct pci_config_window *cfg;
if (acpi_disabled)
return (struct xgene_pcie_port *)(bus->sysdata);
cfg = bus->sysdata;
return (struct xgene_pcie_port *)(cfg->priv);
}
/*
* When the address bit [17:16] is 2'b01, the Configuration access will be
* treated as Type 1 and it will be forwarded to external PCIe device.
*/
static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
{
struct xgene_pcie_port *port = pcie_bus_to_port(bus);
if (bus->number >= (bus->primary + 1))
return port->cfg_base + AXI_EP_CFG_ACCESS;
return port->cfg_base;
}
/*
* For Configuration request, RTDID register is used as Bus Number,
* Device Number and Function number of the header fields.
*/
static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
{
struct xgene_pcie_port *port = pcie_bus_to_port(bus);
unsigned int b, d, f;
u32 rtdid_val = 0;
b = bus->number;
d = PCI_SLOT(devfn);
f = PCI_FUNC(devfn);
if (!pci_is_root_bus(bus))
rtdid_val = (b << 8) | (d << 3) | f;
xgene_pcie_writel(port, RTDID, rtdid_val);
/* read the register back to ensure flush */
xgene_pcie_readl(port, RTDID);
}
/*
* X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
* the translation from PCI bus to native BUS. Entire DDR region
* is mapped into PCIe space using these registers, so it can be
* reached by DMA from EP devices. The BAR0/1 of bridge should be
* hidden during enumeration to avoid the sizing and resource allocation
* by PCIe core.
*/
static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
{
if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
(offset == PCI_BASE_ADDRESS_1)))
return true;
return false;
}
static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
int offset)
{
if ((pci_is_root_bus(bus) && devfn != 0) ||
xgene_pcie_hide_rc_bars(bus, offset))
return NULL;
xgene_pcie_set_rtdid_reg(bus, devfn);
return xgene_pcie_get_cfg_base(bus) + offset;
}
static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
struct xgene_pcie_port *port = pcie_bus_to_port(bus);
if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
PCIBIOS_SUCCESSFUL)
return PCIBIOS_DEVICE_NOT_FOUND;
/*
* The v1 controller has a bug in its Configuration Request
* Retry Status (CRS) logic: when CRS is enabled and we read the
* Vendor and Device ID of a non-existent device, the controller
* fabricates return data of 0xFFFF0001 ("device exists but is not
* ready") instead of 0xFFFFFFFF ("device does not exist"). This
* causes the PCI core to retry the read until it times out.
* Avoid this by not claiming to support CRS.
*/
if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
if (size <= 2)
*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
return PCIBIOS_SUCCESSFUL;
}
#endif
#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
static int xgene_get_csr_resource(struct acpi_device *adev,
struct resource *res)
{
struct device *dev = &adev->dev;
struct resource_entry *entry;
struct list_head list;
unsigned long flags;
int ret;
INIT_LIST_HEAD(&list);
flags = IORESOURCE_MEM;
ret = acpi_dev_get_resources(adev, &list,
acpi_dev_filter_resource_type_cb,
(void *) flags);
if (ret < 0) {
dev_err(dev, "failed to parse _CRS method, error code %d\n",
ret);
return ret;
}
if (ret == 0) {
dev_err(dev, "no IO and memory resources present in _CRS\n");
return -EINVAL;
}
entry = list_first_entry(&list, struct resource_entry, node);
*res = *entry->res;
acpi_dev_free_resource_list(&list);
|