/* Freescale QUICC Engine HDLC Device Driver
*
* Copyright 2016 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/hdlc.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/skbuff.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/stddef.h>
#include <soc/fsl/qe/qe_tdm.h>
#include <uapi/linux/if_arp.h>
#include "fsl_ucc_hdlc.h"
#define DRV_DESC "Freescale QE UCC HDLC Driver"
#define DRV_NAME "ucc_hdlc"
#define TDM_PPPOHT_SLIC_MAXIN
static struct ucc_tdm_info utdm_primary_info = {
.uf_info = {
.tsa = 0,
.cdp = 0,
.cds = 1,
.ctsp = 1,
.ctss = 1,
.revd = 0,
.urfs = 256,
.utfs = 256,
.urfet = 128,
.urfset = 192,
.utfet = 128,
.utftt = 0x40,
.ufpt = 256,
.mode = UCC_FAST_PROTOCOL_MODE_HDLC,
.ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
.tenc = UCC_FAST_TX_ENCODING_NRZ,
.renc = UCC_FAST_RX_ENCODING_NRZ,
.tcrc = UCC_FAST_16_BIT_CRC,
.synl = UCC_FAST_SYNC_LEN_NOT_USED,
},
.si_info = {
#ifdef TDM_PPPOHT_SLIC_MAXIN
.simr_rfsd = 1,
.simr_tfsd = 2,
#else
.simr_rfsd = 0,
.simr_tfsd = 0,
#endif
.simr_crt = 0,
.simr_sl = 0,
.simr_ce = 1,
.simr_fe = 1,
.simr_gm = 0,
},
};
static struct ucc_tdm_info utdm_info[MAX_HDLC_NUM];
static int uhdlc_init(struct ucc_hdlc_private *priv)
{
struct ucc_tdm_info *ut_info;
struct ucc_fast_info *uf_info;
u32 cecr_subblock;
u16 bd_status;
int ret, i;
void *bd_buffer;
dma_addr_t bd_dma_addr;
u32 riptr;
u32 tiptr;
u32 gumr;
ut_info = priv->ut_info;
uf_info = &ut_info->uf_info;
if (priv->tsa) {
uf_info->tsa = 1;
uf_info->ctsp = 1;
}
/* This sets HPM register in CMXUCR register which configures a
* open drain connected HDLC bus
*/
if (priv->hdlc_bus)
uf_info->brkpt_support = 1;
uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
UCC_HDLC_UCCE_TXB) << 16);
ret = ucc_fast_init(uf_info, &priv->uccf);
if (ret) {
dev_err(priv->dev, "Failed to init uccf.");
return ret;
}
priv->uf_regs = priv->uccf->uf_regs;
ucc_fast_disable(priv