blob: 25aa54611774b29077138fd321f1848f7f15343b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
|
/*
* Copyright (C) 2015 Microchip Technology
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _LAN78XX_H
#define _LAN78XX_H
/* USB Vendor Requests */
#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
#define USB_VENDOR_REQUEST_GET_STATS 0xA2
/* Interrupt Endpoint status word bitfields */
#define INT_ENP_EEE_START_TX_LPI_INT BIT(26)
#define INT_ENP_EEE_STOP_TX_LPI_INT BIT(25)
#define INT_ENP_EEE_RX_LPI_INT BIT(24)
#define INT_ENP_RDFO_INT BIT(22)
#define INT_ENP_TXE_INT BIT(21)
#define INT_ENP_TX_DIS_INT BIT(19)
#define INT_ENP_RX_DIS_INT BIT(18)
#define INT_ENP_PHY_INT BIT(17)
#define INT_ENP_DP_INT BIT(16)
#define INT_ENP_MAC_ERR_INT BIT(15)
#define INT_ENP_TDFU_INT BIT(14)
#define INT_ENP_TDFO_INT BIT(13)
#define INT_ENP_UTX_FP_INT BIT(12)
#define TX_PKT_ALIGNMENT 4
#define RX_PKT_ALIGNMENT 4
/* Tx Command A */
#define TX_CMD_A_IGE_ (0x20000000)
#define TX_CMD_A_ICE_ (0x10000000)
#define TX_CMD_A_LSO_ (0x08000000)
#define TX_CMD_A_IPE_ (0x04000000)
#define TX_CMD_A_TPE_ (0x02000000)
#define TX_CMD_A_IVTG_ (0x01000000)
#define TX_CMD_A_RVTG_ (0x00800000)
#define TX_CMD_A_FCS_ (0x00400000)
#define TX_CMD_A_LEN_MASK_ (0x000FFFFF)
/* Tx Command B */
#define TX_CMD_B_MSS_SHIFT_ (16)
#define TX_CMD_B_MSS_MASK_ (0x3FFF0000)
#define TX_CMD_B_MSS_MIN_ ((unsigned short)8)
#define TX_CMD_B_VTAG_MASK_ (0x0000FFFF)
#define TX_CMD_B_VTAG_PRI_MASK_ (0x0000E000)
#define TX_CMD_B_VTAG_CFI_MASK_ (0x00001000)
#define TX_CMD_B_VTAG_VID_MASK_ (0x00000FFF)
/* Rx Command A */
#define RX_CMD_A_ICE_ (0x80000000)
#define RX_CMD_A_TCE_ (0x40000000)
#define RX_CMD_A_CSE_MASK_ (0xC0000000)
#define RX_CMD_A_IPV_ (0x20000000)
#define RX_CMD_A_PID_MASK_ (0x18000000)
#define RX_CMD_A_PID_NONE_IP_ (0x00000000)
#define RX_CMD_A_PID_TCP_IP_ (0x08000000)
#define RX_CMD_A_PID_UDP_IP_ (0x10000000)
#define RX_CMD_A_PID_IP_ (0x18000000)
#define RX_CMD_A_PFF_ (0x04000000)
#define RX_CMD_A_BAM_ (0x02000000)
#define RX_CMD_A_MAM_ (0x01000000)
#define RX_CMD_A_FVTG_ (0x00800000)
#define RX_CMD_A_RED_ (0x00400000)
#define RX_CMD_A_RX_ERRS_MASK_ (0xC03F0000)
#define RX_CMD_A_RWT_ (0x00200000)
#define RX_CMD_A_RUNT_ (0x00100000)
#define RX_CMD_A_LONG_ (0x00080000)
#define RX_CMD_A_RXE_ (0x00040000)
#define RX_CMD_A_DRB_ (0x00020000)
#define RX_CMD_A_FCS_ (0x00010000)
#define RX_CMD_A_UAM_ (0x00008000)
#define RX_CMD_A_ICSM_ (0x00004000)
#define RX_CMD_A_LEN_MASK_ (0x00003FFF)
/* Rx Command B */
#define RX_CMD_B_CSUM_SHIFT_ (16)
#define RX_CMD_B_CSUM_MASK_ (0xFFFF0000)
#define RX_CMD_B_VTAG_MASK_ (0x0000FFFF)
#define RX_CMD_B_VTAG_PRI_MASK_ (0x0000E000)
#define RX_CMD_B_VTAG_CFI_MASK_ (0x00001000)
#define RX_CMD_B_VTAG_VID_MASK_ (0x00000FFF)
/* Rx Command C */
#define RX_CMD_C_WAKE_SHIFT_ (15)
#define RX_CMD_C_WAKE_ (0x8000)
#define RX_CMD_C_REF_FAIL_SHIFT_ (14)
#define RX_CMD_C_REF_FAIL_ (0x4000)
/* SCSRs */
#define NUMBER_OF_REGS (193)
#define ID_REV (0x00)
#define ID_REV_CHIP_ID_MASK_ (0xFFFF0000)
#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
#define ID_REV_CHIP_ID_7800_ (0x7800)
#define ID_REV_CHIP_ID_7850_ (0x7850)
#define ID_REV_CHIP_ID_7801_ (0x7801)
#define FPGA_REV (0x04)
#define FPGA_REV_MINOR_MASK_ (0x0000FF00)
#define FPGA_REV_MAJOR_MASK_ (0x000000FF)
#define INT_STS (0x0C)
#define INT_STS_CLEAR_ALL_ (0xFFFFFFFF)
#define INT_STS_EEE_TX_LPI_STRT_ (0x04000000)
#define INT_STS_EEE_TX_LPI_STOP_ (0x02000000)
#define INT_STS_EEE_RX_LPI_ (0x01000000)
#define INT_STS_RDFO_ (0x00400000)
#define INT_STS_TXE_ (0x00200000)
#define INT_STS_TX_DIS_ (0x00080000)
#define INT_STS_RX_DIS_ (0x00040000)
#define INT_STS_PHY_INT_ (0x00020000)
#define INT_STS_DP_INT_ (0x00010000)
#define INT_STS_MAC_ERR_ (0x00008000)
#define INT_STS_TDFU_ (0x00004000)
#define INT_STS_TDFO_ (0x00002000)
#define INT_STS_UFX_FP_ (0x00001000)
#define INT_STS_GPIO_MASK_ (0x00000FFF)
#define INT_STS_GPIO11_ (0x00000800)
#define INT_STS_GPIO10_ (0x00000400)
#define INT_STS_GPIO9_ (0x00000200)
#define INT_STS_GPIO8_ (0x00000100)
#define INT_STS_GPIO7_ (0x00000080)
#define INT_STS_GPIO6_ (0x00000040)
#define INT_STS_GPIO5_ (0x00000020)
#define INT_STS_GPIO4_ (0x00000010)
#define INT_STS_GPIO3_ (0x00000008)
#define INT_STS_GPIO2_ (0x00000004)
#define INT_STS_GPIO1_ (0x00000002)
#define INT_STS_GPIO0_ (0x00000001)
#define HW_CFG (0x010)
#define HW_CFG_CLK125_EN_ (0x02000000)
#define HW_CFG_REFCLK25_EN_ (0x01000000)
#define HW_CFG_LED3_EN_ (0x00800000)
#define HW_CFG_LED2_EN_ (0x00400000)
#define HW_CFG_LED1_EN_ (0x00200000)
#define HW_CFG_LED0_EN_ (0x00100000)
#define HW_CFG_EEE_PHY_LUSU_ (0x00020000)
#define HW_CFG_EEE_TSU_ (0x00010000)
#define HW_CFG_NETDET_STS_ (0x00008000)
#define HW_CFG_NETDET_EN_ (0x00004000)
#define HW_CFG_EEM_ (0x00002000)
#define HW_CFG_RST_PROTECT_ (0x00001000)
#define HW_CFG_CONNECT_BUF_ (0x00000400)
#define HW_CFG_CONNECT_EN_ (0x00000200)
#define HW_CFG_CONNECT_POL_ (0x00000100)
#define HW_CFG_SUSPEND_N_SEL_MASK_ (0x000000C0)
#define HW_CFG_SUSPEND_N_SEL_2 (0x00000000)
#define HW_CFG_SUSPEND_N_SEL_12N (0x00000040)
#define HW_CFG_SUSPEND_N_SEL_012N (0x00000080)
#define HW_CFG_SUSPEND_N_SEL_0123N (0x000000C0)
#define HW_CFG_SUSPEND_N_POL_ (0x00000020)
#define HW_CFG_MEF_ (0x00000010)
#define HW_CFG_ETC_ (0x00000008)
#define HW_CFG_LRST_ (0x00000002)
#define HW_CFG_SRST_ (0x00000001)
#define PMT_CTL (0x014)
#define PMT_CTL_EEE_WAKEUP_EN_ (0x00002000)
#define PMT_CTL_EEE_WUPS_ (0x00001000)
#define PMT_CTL_MAC_SRST_ (0x00000800)
#define PMT_CTL_PHY_PWRUP_ (0x00000400)
#define PMT_CTL_RES_CLR_WKP_MASK_ (0x00000300)
#define PMT_CTL_RES_CLR_WKP_STS_ (0x00000200)
#define PMT_CTL_RES_CLR_WKP_EN_ (0x00000100)
#define PMT_CTL_READY_ (0x00000080)
#define PMT_CTL_SUS_MODE_MASK_ (0x00000060)
#define PMT_CTL_SUS_MODE_0_ (0x00000000)
#define PMT_CTL_SUS_MODE_1_ (0x00000020)
#define PMT_CTL_SUS_MODE_2_ (0x00000040)
#define PMT_CTL_SUS_MODE_3_ (0x00000060)
#define PMT_CTL_PHY_RST_ (0x00000010)
#define PMT_CTL_WOL_EN_ (0x00000008)
#define PMT_CTL_PHY_WAKE_EN_ (0x00000004)
#define PMT_CTL_WUPS_MASK_ (0x00000003)
#define PMT_CTL_WUPS_MLT_ (0x00000003)
#define PMT_CTL_WUPS_MAC_ (0x00000002)
#define PMT_CTL_WUPS_PHY_ (0x00000001)
#define GPIO_CFG0 (0x018)
#define GPIO_CFG0_GPIOEN_MASK_ (0x0000F000)
#define GPIO_CFG0_GPIOEN3_ (0x00008000)
#define GPIO_CFG0_GPIOEN2_ (0x00004000)
#define GPIO_CFG0_GPIOEN1_ (0x00002000)
#define GPIO_CFG0_GPIOEN0_ (0x00001000)
#define GPIO_CFG0_GPIOBUF_MASK_ (0x00000F00)
#define GPIO_CFG0_GPIOBUF3_ (0x00000800)
#define GPIO_CFG0_GPIOBUF2_ (0x00000400)
#define GPIO_CFG0_GPIOBUF1_ (0x00000200)
#define GPIO_CFG0_GPIOBUF0_ (0x00000100)
#define GPIO_CFG0_GPIODIR_MASK_ (0x000000F0)
#define GPIO_CFG0_GPIODIR3_ (0x00000080)
#define GPIO_CFG0_GPIODIR2_ (0x00000040)
#define GPIO_CFG0_GPIODIR1_ (0x00000020)
#define GPIO_CFG0_GPIODIR0_ (0x00000010)
#define GPIO_CFG0_GPIOD_MASK_ (0x0000000F)
#define GPIO_CFG0_GPIOD3_ (0x00000008)
#define GPIO_CFG0_GPIOD2_ (0x00000004)
#define GPIO_CFG0_GPIOD1_ (0x00000002)
#define GPIO_CFG0_GPIOD0_ (0x00000001)
#define GPIO_CFG1 (0x01C)
#define GPIO_CFG1_GPIOEN_MASK_ (0xFF000000)
#define GPIO_CFG1_GPIOEN11_ (0x80000000)
#define GPIO_CFG1_GPIOEN10_ (0x40000000)
#define GPIO_CFG1_GPIOEN9_ (0x20000000)
#define GPIO_CFG1_GPIOEN8_ (0x10000000)
#define GPIO_CFG1_GPIOEN7_ (0x08000000)
#define GPIO_CFG1_GPIOEN6_ (0x04000000)
#define GPIO_CFG1_GPIOEN5_ (0x02000000)
#define GPIO_CFG1_GPIOEN4_ (0x01000000)
#define GPIO_CFG1_GPIOBUF_MASK_ (0x00FF0000)
#define GPIO_CFG1_GPIOBUF11_ (0x00800000)
#define GPIO_CFG1_GPIOBUF10_ (0x00400000)
#define GPIO_CFG1_GPIOBUF9_ (0x00200000)
#define GPIO_CFG1_GPIOBUF8_ (0x00100000)
#define GPIO_CFG1_GPIOBUF7_ (0x00080000)
#define GPIO_CFG1_GPIOBUF6_ (0x00040000)
#define GPIO_CFG1_GPIOBUF5_ (0x00020000)
#define GPIO_CFG1_GPIOBUF4_ (0x00010000)
#define GPIO_CFG1_GPIODIR_MASK_ (0x0000FF00)
#define GPIO_CFG1_GPIODIR11_ (0x00008000)
#define GPIO_CFG1_GPIODIR10_ (0x00004000)
#define GPIO_CFG1_GPIODIR9_ (0x00002000)
#define GPIO_CFG1_GPIODIR8_ (0x00001000)
#define GPIO_CFG1_GPIODIR7_ (0x00000800)
#define GPIO_CFG1_GPIODIR6_ (0x00000400)
#define GPIO_CFG1_GPIODIR5_ (0x00000200)
#define GPIO_CFG1_GPIODIR4_ (0x00000100)
#define GPIO_CFG1_GPIOD_MASK_ (0x000000FF)
#define GPIO_CFG1_GPIOD11_ (0x00000080)
#define GPIO_CFG1_GPIOD10_ (0x00000040)
#define GPIO_CFG1_GPIOD9_ (0x00000020)
#define GPIO_CFG1_GPIOD8_ (0x00000010)
#define GPIO_CFG1_GPIOD7_ (0x00000008)
#define GPIO_CFG1_GPIOD6_ (0x00000004)
#define GPIO_CFG1_GPIOD6_ (0x00000004)
#define GPIO_CFG1_GPIOD5_ (0x00000002)
#define GPIO_CFG1_GPIOD4_ (0x00000001)
#define GPIO_WAKE (0x020)
#define GPIO_WAKE_GPIOPOL_MASK_ (0x0FFF0000)
#define GPIO_WAKE_GPIOPOL11_ (0x08000000)
#define GPIO_WAKE_GPIOPOL10_ (0x04000000)
#define GPIO_WAKE_GPIOPOL9_ (0x02000000)
#define GPIO_WAKE_GPIOPOL8_ (0x01000000)
#define GPIO_WAKE_GPIOPOL7_ (0x00800000)
#define GPIO_WAKE_GPIOPOL6_ (0x00400000)
#define GPIO_WAKE_GPIOPOL5_ (0x00200000)
#define GPIO_WAKE_GPIOPOL4_ (0x00100000)
#define GPIO_WAKE_GPIOPOL3_ (0x00080000)
#define GPIO_WAKE_GPIOPOL2_ (0x00040000)
#define GPIO_WAKE_GPIOPOL1_ (0x00020000)
#define GPIO_WAKE_GPIOPOL0_ (0x00010000)
#define GPIO_WAKE_GPIOWK_MASK_ (0x00000FFF)
#define GPIO_WAKE_GPIOWK11_ (0x00000800)
#define GPIO_WAKE_GPIOWK10_ (0x00000400)
#define GPIO_WAKE_GPIOWK9_ (0x00000200)
#define GPIO_WAKE_GPIOWK8_ (0x00000100)
#define GPIO_WAKE_GPIOWK7_ (0x00000080)
#define GPIO_WAKE_GPIOWK6_ (0x00000040)
#define GPIO_WAKE_GPIOWK5_ (0x00000020)
#define GPIO_WAKE_GPIOWK4_ (0x00000010)
#define GPIO_WAKE_GPIOWK3_ (0x00000008)
#define GPIO_WAKE_GPIOWK2_ (0x00000004)
#define GPIO_WAKE_GPIOWK1_ (0x00000002)
#define GPIO_WAKE_GPIOWK0_ (0x00000001)
#define DP_SEL (0x024)
#define DP_SEL_DPRDY_ (0x80000000)
#define DP_SEL_RSEL_MASK_ (0x0000000F)
#define DP_SEL_RSEL_USB_PHY_CSRS_ (0x0000000F)
#define DP_SEL_RSEL_OTP_64BIT_ (0x00000009)
#define DP_SEL_RSEL_OTP_8BIT_ (0x00000008)
#define DP_SEL_RSEL_UTX_BUF_RAM_ (0x00000007)
#define DP_SEL_RSEL_DESC_RAM_ (0x00000005)
#define DP_SEL_RSEL_TXFIFO_ (0x00000004)
#define DP_SEL_RSEL_RXFIFO_ (0x00000003)
#define DP_SEL_RSEL_LSO_ (0x00000002)
#define DP_SEL_RSEL_VLAN_DA_ (0x00000001)
#define DP_SEL_RSEL_URXBUF_ (0x00000000)
#define DP_SEL_VHF_HASH_LEN (16)
#define DP_SEL_VHF_VLAN_LEN (128)
#define DP_CMD (0x028)
#define DP_CMD_WRITE_ (0x00000001)
#define DP_CMD_READ_ (0x00000000)
#define DP_ADDR (0x02C)
#define DP_ADDR_MASK_ (0x00003FFF)
#define DP_DATA (0x030)
#define E2P_CMD (0x040)
#define E2P_CMD_EPC_BUSY_ (0x80000000)
#define E2P_CMD_EPC_CMD_MASK_ (0x70000000)
#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000)
#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000)
#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000)
#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000)
#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000)
#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
#define E2P_CMD_EPC_TIMEOUT_ (0x00000400)
#define E2P_CMD_EPC_DL_ (0x00000200)
#define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
#define E2P_DATA (0x044)
#define E2P_DATA_EEPROM_DATA_MASK_ (0x000000FF)
#define BOS_ATTR (0x050)
#define BOS_ATTR_BLOCK_SIZE_MASK_ (0x000000FF)
#define SS_ATTR (0x054)
#define SS_ATTR_POLL_INT_MASK_ (0x00FF0000)
#define SS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00)
#define SS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF)
#define HS_ATTR (0x058)
#define HS_ATTR_POLL_INT_MASK_ (0x00FF0000)
#define HS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00)
#define HS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF)
#define FS_ATTR (0x05C)
#define FS_ATTR_POLL_INT_MASK_ (0x00FF0000)
#define FS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00)
#define FS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF)
#define STR_ATTR0 (0x060)
#define STR_ATTR0_CFGSTR_DESC_SIZE_MASK_ (0xFF000000)
#define STR_ATTR0_SERSTR_DESC_SIZE_MASK_ (0x00FF0000)
#define STR_ATTR0_PRODSTR_DESC_SIZE_MASK_ (0x0000FF00)
#define STR_ATTR0_MANUF_DESC_SIZE_MASK_ (0x000000FF)
#define STR_ATTR1 (0x064)
#define STR_ATTR1_INTSTR_DESC_SIZE_MASK_ (0x000000FF)
#define STR_FLAG_ATTR (0x068)
#define STR_FLAG_ATTR_PME_FLAGS_MASK_ (0x000000FF)
#define USB_CFG0 (0x080)
#define USB_CFG_LPM_RESPONSE_ (0x80000000)
#define USB_CFG_LPM_CAPABILITY_ (0x40000000)
#define USB_CFG_LPM_ENBL_SLPM_ (0x20000000)
#define USB_CFG_HIRD_THR_MASK_ (0x1F000000)
#define USB_CFG_HIRD_THR_960_ (0x1C000000)
#define USB_CFG_HIRD_THR_885_ (0x1B000000)
#define USB_CFG_HIRD_THR_810_ (0x1A000000)
#define USB_CFG_HIRD_THR_735_ (0x19000000)
#define USB_CFG_HIRD_THR_660_ (0x18000000)
#define USB_CFG_HIRD_THR_585_ (0x17000000)
#define USB_CFG_HIRD_THR_510_ (0x16000000)
#define USB_CFG_HIRD_THR_435_ (0x15000000)
#define USB_CFG_HIRD_THR_360_ (0x14000000)
#define USB_CFG_HIRD_THR_285_ (0x13000000)
#define USB_CFG_HIRD_THR_210_ (0x12000000)
#define USB_CFG_HIRD_THR_135_ (0x11000000)
#define USB_CFG_HIRD_THR_60_ (0x10000000)
#define USB_CFG_MAX_BURST_BI_MASK_ (0x00F00000)
#define USB_CFG_MAX_BURST_BO_MASK_ (0x000F0000)
#define USB_CFG_MAX_DEV_SPEED_MASK_ (0x0000E000)
#define USB_CFG_MAX_DEV_SPEED_SS_ (0x00008000)
#define USB_CFG_MAX_DEV_SPEED_HS_ (0x00000000)
#define USB_CFG_MAX_DEV_SPEED_FS_ (0x00002000)
#define USB_CFG_PHY_BOOST_MASK_ (0x00000180)
#define USB_CFG_PHY_BOOST_PLUS_12_ (0x00000180)
#define USB_CFG_PHY_BOOST_PLUS_8_ (0x00000100)
#define USB_CFG_PHY_BOOST_PLUS_4_ (0x00000080)
#define USB_CFG_PHY_BOOST_NORMAL_ (0x00000000)
#define USB_CFG_BIR_ (0x00000040)
#define USB_CFG_BCE_ (0x00000020)
#define USB_CFG_PORT_SWAP_ (0x00000010)
#define USB_CFG_LPM_EN_ (0x00000008)
#define USB_CFG_RMT_WKP_ (0x00000004)
#define USB_CFG_PWR_SEL_ (0x00000002)
#define USB_CFG_STALL_BO_DIS_ (0x00000001)
#define USB_CFG1 (0x084)
#define USB_CFG1_U1_TIMEOUT_MASK_ (0xFF000000)
#define USB_CFG1_U2_TIMEOUT_MASK_ (0x00FF0000)
#define USB_CFG1_HS_TOUT_CAL_MASK_ (0x0000E000)
#define USB_CFG1_DEV_U2_INIT_EN_ (0x00001000)
#define USB_CFG1_DEV_U2_EN_ (0x00000800)
#define USB_CFG1_DEV_U1_INIT_EN_ (0x00000400)
#define USB_CFG1_DEV_U1_EN_ (0x00000200)
#define USB_CFG1_LTM_ENABLE_ (0x00000100)
#define USB_CFG1_FS_TOUT_CAL_MASK_ (0x00000070)
#define USB_CFG1_SCALE_DOWN_MASK_ (0x00000003)
#define USB_CFG1_SCALE_DOWN_MODE3_ (0x00000003)
#define USB_CFG1_SCALE_DOWN_MODE2_ (0x00000002)
#define USB_CFG1_SCALE_DOWN_MODE1_ (0x00000001)
#define USB_CFG1_SCALE_DOWN_MODE0_ (0x00000000)
#define USB_CFG2 (0x088)
#define USB_CFG2_SS_DETACH_TIME_MASK_ (0xFFFF0000)
#define USB_CFG2_HS_DETACH_TIME_MASK_ (0x0000FFFF)
#define BURST_CAP (0x090)
#define BURST_CAP_SIZE_MASK_ (0x000000FF)
#define BULK_IN_DLY (0x094)
#define BULK_IN_DLY_MASK_ (0x0000FFFF)
#define INT_EP_CTL (0x098)
#define INT_EP_INTEP_ON_ (0x80000000)
#define INT_STS_EEE_TX_LPI_STRT_EN_ (0x04000000)
#define INT_STS_EEE_TX_LPI_STOP_EN_ (0x02000000)
#define INT_STS_EEE_RX_LPI_EN_ (0x01000000)
#define INT_EP_RDFO_EN_ (0x00400000)
#define INT_EP_TXE_EN_ (0x00200000)
#define INT_EP_TX_DIS_EN_ (0x00080000)
#define INT_EP_RX_DIS_EN_ (0x00040000)
#define INT_EP_PHY_INT_EN_ (0x00020000)
#define INT_EP_DP_INT_EN_ (0x00010000)
#define INT_EP_MAC_ERR_EN_ (0x00008000)
#define INT_EP_TDFU_EN_ (0x00004000)
#define INT_EP_TDFO_EN_ (0x00002000)
#define INT_EP_UTX_FP_EN_ (0x00001000)
#define INT_EP_GPIO_EN_MASK_ (0x00000FFF)
#define PIPE_CTL (0x09C)
#define PIPE_CTL_TXSWING_ (0x00000040)
#define PIPE_CTL_TXMARGIN_MASK_ (0x00000038)
#define PIPE_CTL_TXDEEMPHASIS_MASK_ (0x00000006)
#define PIPE_CTL_ELASTICITYBUFFERMODE_ (0x00000001)
#define U1_LATENCY (0xA0)
#define U2_LATENCY (0xA4)
#define USB_STATUS (0x0A8)
#define USB_STATUS_REMOT
|