/*
* JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
*
* Copyright 2008 JMicron Technology Corporation
* http://www.jmicron.com/
* Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
*
* Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __JME_H_INCLUDED__
#define __JME_H_INCLUDED__
#include <linux/interrupt.h>
#define DRV_NAME "jme"
#define DRV_VERSION "1.0.8"
#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
/*
* Message related definitions
*/
#define JME_DEF_MSG_ENABLE \
(NETIF_MSG_PROBE | \
NETIF_MSG_LINK | \
NETIF_MSG_RX_ERR | \
NETIF_MSG_TX_ERR | \
NETIF_MSG_HW)
#ifdef TX_DEBUG
#define tx_dbg(priv, fmt, args...) \
printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
#else
#define tx_dbg(priv, fmt, args...) \
do { \
if (0) \
printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
} while (0)
#endif
/*
* Extra PCI Configuration space interface
*/
#define PCI_DCSR_MRRS 0x59
#define PCI_DCSR_MRRS_MASK 0x70
enum pci_dcsr_mrrs_vals {
MRRS_128B = 0x00,
MRRS_256B = 0x10,
MRRS_512B = 0x20,
MRRS_1024B = 0x30,
MRRS_2048B = 0x40,
MRRS_4096B = 0x50,
};
#define PCI_SPI 0xB0
enum pci_spi_bits {
SPI_EN = 0x10,
SPI_MISO = 0x08,
SPI_MOSI = 0x04,
SPI_SCLK = 0x02,
SPI_CS = 0x01,
};
struct jme_spi_op {
void __user *uwbuf;
void __user *urbuf;
__u8 wn; /* Number of write actions */
__u8 rn; /* Number of read actions */
__u8 bitn; /* Number of bits per action */
__u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
__u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
/* Internal use only */
u8 *kwbuf;
u8 *krbuf;
u8 sr;
u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
};
enum jme_spi_op_bits {
SPI_MODE_CPHA = 0x01,
SPI_MODE_CPOL = 0x02,
SPI_MODE_DUP = 0x80,
};
#define HALF_US 500 /* 500 ns */
#define PCI_PRIV_PE1 0xE4
enum pci_priv_pe1_bit_masks {
PE1_ASPMSUPRT = 0x00000003, /*
* RW:
* Aspm_support[1:0]
* (R/W Port of 5C[11:10])
*/
PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
PE1_GPREG0 = 0x0000FF00, /*
* SRW:
* Cfg_gp_reg0
* [7:6] phy_giga BG control
* [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
* [4:0] Reserved
*/
PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
PE1_REVID = 0xFF000000, /* RO: Rev ID */
};
enum pci_priv_pe1_values {
PE1_GPREG0_ENBG = 0x00000000, /* en BG */
PE1_GPREG0_PDD3COLD = 0x00004000,