// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 1999 - 2018 Intel Corporation. */
#include "ixgbe.h"
#include "ixgbe_sriov.h"
#ifdef CONFIG_IXGBE_DCB
/**
* ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
* @adapter: board private structure to initialize
*
* Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
* will also try to cache the proper offsets if RSS/FCoE are enabled along
* with VMDq.
*
**/
static bool ixgbe_cache_ring_dcb_sriov(struct ixgbe_adapter *adapter)
{
#ifdef IXGBE_FCOE
struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE];
#endif /* IXGBE_FCOE */
struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
int i;
u16 reg_idx, pool;
u8 tcs = adapter->hw_tcs;
/* verify we have DCB queueing enabled before proceeding */
if (tcs <= 1)
return false;
/* verify we have VMDq enabled before proceeding */
if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
return false;
/* start at VMDq register offset for SR-IOV enabled setups */
reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) {
/* If we are greater than indices move to next pool */
if ((reg_idx & ~vmdq->mask) >= tcs) {
pool++;
reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
}
adapter->rx_ring[i]->reg_idx = reg_idx;
adapter->rx_ring[i]->netdev = pool ? NULL : adapter->netdev;
}
reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) {
/* If we are greater than indices move to next pool */
if ((reg_idx & ~vmdq->mask) >= tcs)
reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
adapter->tx_ring[i]->reg_idx = reg_idx;
}
#ifdef IXGBE_FCOE
/* nothing to do if FCoE is disabled */
if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
return