/* SPDX-License-Identifier: GPL-2.0 *//* Copyright (c) 2018, Intel Corporation. */#ifndef _ICE_ADMINQ_CMD_H_#define _ICE_ADMINQ_CMD_H_/* This header file defines the Admin Queue commands, error codes and * descriptor format. It is shared between Firmware and Software. */#define ICE_MAX_VSI 768#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728structice_aqc_generic{__le32param0;__le32param1;__le32addr_high;__le32addr_low;};/* Get version (direct 0x0001) */structice_aqc_get_ver{__le32rom_ver;__le32fw_build;u8fw_branch;u8fw_major;u8fw_minor;u8fw_patch;u8api_branch;u8api_major;u8api_minor;u8api_patch;};/* Queue Shutdown (direct 0x0003) */structice_aqc_q_shutdown{#define ICE_AQC_DRIVER_UNLOADING BIT(0)__le32driver_unloading;u8reserved[12];};/* Request resource ownership (direct 0x0008) * Release resource ownership (direct 0x0009) */structice_aqc_req_res{__le16res_id;#define ICE_AQC_RES_ID_NVM 1#define ICE_AQC_RES_ID_SDP 2#define ICE_AQC_RES_ID_CHNG_LOCK 3#define ICE_AQC_RES_ID_GLBL_LOCK 4__le16access_type;#define ICE_AQC_RES_ACCESS_READ 1#define ICE_AQC_RES_ACCESS_WRITE 2/* Upon successful completion, FW writes this value and driver is * expected to release resource before timeout. This value is provided * in milliseconds. */__le32timeout;#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000/* For SDP: pin id of the SDP */__le32res_number;/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */__le16status;#define ICE_AQ_RES_GLBL_SUCCESS 0#define ICE_AQ_RES_GLBL_IN_PROG 1#define ICE_AQ_RES_GLBL_DONE 2u8reserved[2];};/* Get function capabilities (indirect 0x000A) * Get device capabilities (indirect 0x000B) */structice_aqc_list_caps{u8cmd_flags;u8pf_index;u8reserved[2];__le32count;__le32addr_high;__le32addr_low;};/* Device/Function buffer entry, repeated per reported capability */structice_aqc_list_caps_elem{__le16cap;#define ICE_AQC_CAPS_VSI 0x0017#define ICE_AQC_CAPS_RSS 0x0040#define ICE_AQC_CAPS_RXQS 0x0041#define ICE_AQC_CAPS_TXQS 0x0042#define ICE_AQC_CAPS_MSIX 0x0043#define ICE_AQC_CAPS_MAX_MTU 0x0047u8major_ver;u8minor_ver;/* Number of resources described by this capability */__le32number;/* Only meaningful for some types of resources */__le32logical_id;/* Only meaningful for some types of resources */__le32phys_id;__le64rsvd1;__le64rsvd2;};/* Manage MAC address, read command - indirect (0x0107) * This struct is also used for the response */structice_aqc_manage_ma