path: root/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

/* SPDX-License-Identifier: GPL-2.0+ */
// Copyright (c) 2016-2017 Hisilicon Limited.

#ifndef __HCLGE_MAIN_H
#define __HCLGE_MAIN_H
#include <linux/fs.h>
#include <linux/types.h>
#include <linux/phy.h>
#include <linux/if_vlan.h>
#include <linux/kfifo.h>

#include "hclge_cmd.h"
#include "hnae3.h"

#define HCLGE_MOD_VERSION "1.0"
#define HCLGE_DRIVER_NAME "hclge"

#define HCLGE_MAX_PF_NUM		8

#define HCLGE_RD_FIRST_STATS_NUM        2
#define HCLGE_RD_OTHER_STATS_NUM        4

#define HCLGE_INVALID_VPORT 0xffff

#define HCLGE_PF_CFG_BLOCK_SIZE		32
#define HCLGE_PF_CFG_DESC_NUM \
	(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)

#define HCLGE_VECTOR_REG_BASE		0x20000
#define HCLGE_MISC_VECTOR_REG_BASE	0x20400

#define HCLGE_VECTOR_REG_OFFSET		0x4
#define HCLGE_VECTOR_VF_OFFSET		0x100000

#define HCLGE_CMDQ_TX_ADDR_L_REG	0x27000
#define HCLGE_CMDQ_TX_ADDR_H_REG	0x27004
#define HCLGE_CMDQ_TX_DEPTH_REG		0x27008
#define HCLGE_CMDQ_TX_TAIL_REG		0x27010
#define HCLGE_CMDQ_TX_HEAD_REG		0x27014
#define HCLGE_CMDQ_RX_ADDR_L_REG	0x27018
#define HCLGE_CMDQ_RX_ADDR_H_REG	0x2701C
#define HCLGE_CMDQ_RX_DEPTH_REG		0x27020
#define HCLGE_CMDQ_RX_TAIL_REG		0x27024
#define HCLGE_CMDQ_RX_HEAD_REG		0x27028
#define HCLGE_CMDQ_INTR_SRC_REG		0x27100
#define HCLGE_CMDQ_INTR_STS_REG		0x27104
#define HCLGE_CMDQ_INTR_EN_REG		0x27108
#define HCLGE_CMDQ_INTR_GEN_REG		0x2710C

/* bar registers for common func */
#define HCLGE_VECTOR0_OTER_EN_REG	0x20600
#define HCLGE_RAS_OTHER_STS_REG		0x20B00
#define HCLGE_FUNC_RESET_STS_REG	0x20C00
#define HCLGE_GRO_EN_REG		0x28000

/* bar registers for rcb */
#define HCLGE_RING_RX_ADDR_L_REG	0x80000
#define HCLGE_RING_RX_ADDR_H_REG	0x80004
#define HCLGE_RING_RX_BD_NUM_REG	0x80008
#define HCLGE_RING_RX_BD_LENGTH_REG	0x8000C
#define HCLGE_RING_RX_MERGE_EN_REG	0x80014
#define HCLGE_RING_RX_TAIL_REG		0x80018
#define HCLGE_RING_RX_HEAD_REG		0x8001C
#define HCLGE_RING_RX_FBD_NUM_REG	0x80020
#define HCLGE_RING_RX_OFFSET_REG	0x80024
#define HCLGE_RING_RX_FBD_OFFSET_REG	0x80028
#define HCLGE_RING_RX_STASH_REG		0x80030
#define HCLGE_RING_RX_BD_ERR_REG	0x80034
#define HCLGE_RING_TX_ADDR_L_REG	0x80040
#define HCLGE_RING_TX_ADDR_H_REG	0x80044
#define HCLGE_RING_TX_BD_NUM_REG	0x80048
#define HCLGE_RING_TX_PRIORITY_REG	0x8004C
#define HCLGE_RING_TX_TC_REG		0x80050
#define HCLGE_RING_TX_MERGE_EN_REG	0x80054
#define HCLGE_RING_TX_TAIL_REG		0x80058
#define HCLGE_RING_TX_HEAD_REG		0x8005C
#define HCLGE_RING_TX_FBD_NUM_REG	0x80060
#define HCLGE_RING_TX_OFFSET_REG	0x80064
#define HCLGE_RING_TX_EBD_NUM_REG	0x80068
#define HCLGE_RING_TX_EBD_OFFSET_REG	0x80070
#define HCLGE_RING_TX_BD_ERR_REG	0x80074
#define HCLGE_RING_EN_REG		0x80090

/* bar registers for tqp interrupt */
#define HCLGE_TQP_INTR_CTRL_REG		0x20000
#define HCLGE_TQP_INTR_GL0_REG		0x20100
#define HCLGE_TQP_INTR_GL1_REG		0x20200
#define HCLGE_TQP_INTR_GL2_REG		0x20300
#define HCLGE_TQP_INTR_RL_REG		0x20900

#define HCLGE_RSS_IND_TBL_SIZE		512
#define HCLGE_RSS_SET_BITMAP_MSK	GENMASK(15, 0)
#define HCLGE_RSS_KEY_SIZE		40
#define HCLGE_RSS_HASH_ALGO_TOEPLITZ	0
#define HCLGE_RSS_HASH_ALGO_SIMPLE	1
#define HCLGE_RSS_HASH_ALGO_SYMMETRIC	2
#define HCLGE_RSS_HASH_ALGO_MASK	GENMASK(3, 0)
#define HCLGE_RSS_CFG_TBL_NUM \
	(HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)

#define HCLGE_RSS_INPUT_TUPLE_OTHER	GENMASK(3, 0)
#define HCLGE_RSS_INPUT_TUPLE_SCTP	GENMASK(4, 0)
#define HCLGE_D_PORT_BIT		BIT(0)
#define HCLGE_S_PORT_BIT		BIT(1)
#define HCLGE_D_IP_BIT			BIT(2)
#define HCLGE_S_IP_BIT			BIT(3)
#define HCLGE_V_TAG_BIT			BIT(4)

#define HCLGE_RSS_TC_SIZE_0		1
#define HCLGE_RSS_TC_SIZE_1		2
#define HCLGE_RSS_TC_SIZE_2		4
#define HCLGE_RSS_TC_SIZE_3		8
#define HCLGE_RSS_TC_SIZE_4		16
#define HCLGE_RSS_TC_SIZE_5		32
#define HCLGE_RSS_TC_SIZE_6		64
#define HCLGE_RSS_TC_SIZE_7		128

#define HCLGE_UMV_TBL_SIZE		3072
#define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
	(HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)

#define HCLGE_TQP_RESET_TRY_TIMES	200

#define HCLGE_PHY_PAGE_MDIX		0
#define HCLGE_PHY_PAGE_COPPER		0

/* Page Selection Reg. */
#define HCLGE_PHY_PAGE_REG		22

/* Copper Specific Control Register */
#define HCLGE_PHY_CSC_REG		16

/* Copper Specific Status Register */
#define HCLGE_PHY_CSS_REG		17

#define HCLGE_PHY_MDIX_CTRL_S		5
#define HCLGE_PHY_MDIX_CTRL_M		GENMASK(6, 5)

#define HCLGE_PHY_MDIX_STATUS_B		6
#define HCLGE_PHY_SPEED_DUP_RESOLVE_B	11

/* Factor used to calculate offset and bitmap of VF num */
#define HCLGE_VF_NUM_PER_CMD           64
#define HCLGE_VF_NUM_PER_BYTE          8

enum HLCGE_PORT_TYPE {
	HOST_PORT,
	NETWORK_PORT
};

#define PF_VPORT_ID			0

#define HCLGE_PF_ID_S			0
#define HCLGE_PF_ID_M			GENMASK(2, 0)
#define HCLGE_VF_ID_S			3
#define HCLGE_VF_ID_M			GENMASK(10, 3)
#define HCLGE_PORT_TYPE_B		11
#define HCLGE_NETWORK_PORT_ID_S		0
#define HCLGE_NETWORK_PORT_ID_M		GENMASK(3, 0)

/* Reset related Registers */
#define HCLGE_PF_OTHER_INT_REG		0x20600
#define HCLGE_MISC_RESET_STS_REG	0x20700
#define HCLGE_MISC_VECTOR_INT_STS	0x20800
#define HCLGE_GLOBAL_RESET_REG		0x20A00
#define HCLGE_GLOBAL_RESET_BIT		0
#define HCLGE_CORE_RESET_BIT		1
#define HCLGE_IMP_RESET_BIT		2
#define HCLGE_RESET_INT_M		GENMASK(7, 5)
#define HCLGE_FUN_RST_ING		0x20C00
#define HCLGE_FUN_RST_ING_B		0

/* Vector0 register bits define */
#define HCLGE_VECTOR0_GLOBALRESET_INT_B	5
#define HCLGE_VECTOR0_CORERESET_INT_B	6
#define HCLGE_VECTOR0_IMPRESET_INT_B	7

/* Vector0 interrupt CMDQ event source register(RW) */
#define HCLGE_VECTOR0_CMDQ_SRC_REG	0x27100
/* CMDQ register bits for RX event(=MBX event) */
#define HCLGE_VECTOR0_RX_CMDQ_INT_B	1

#define HCLGE_VECTOR0_IMP_RESET_INT_B	1
#define HCLGE_VECTOR0_IMP_CMDQ_ERR_B	4U
#define HCLGE_VECTOR0_IMP_RD_POISON_B	5U

#define HCLGE_MAC_DEFAULT_FRAME \
	(ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
#define HCLGE_MAC_MIN_FRAME		64
#define HCLGE_MAC_MAX_FRAME		9728

#define HCLGE_SUPPORT_1G_BIT		BIT(0)
#define HCLGE_SUPPORT_10G_BIT		BIT(1)
#define HCLGE_SUPPORT_25G_BIT		BIT(2)
#define HCLGE_SUPPORT_50G_BIT		BIT(3)
#define HCLGE_SUPPORT_100G_BIT		BIT(4)
/* to be compatible with exsit board */
#define HCLGE_SUPPORT_40G_BIT		BIT(5)
#define HCLGE_SUPPORT_100M_BIT		BIT(6)
#define HCLGE_SUPPORT_10M_BIT		BIT(7)
#define HCLGE_SUPPORT_GE \
	(HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)

enum HCLGE_DEV_STATE {
	HCLGE_STATE_REINITING,
	HCLGE_STATE_DOWN,
	HCLGE_STATE_DISABLED,
	HCLGE_STATE_REMOVING,
	HCLGE_STATE_NIC_REGISTERED,
	HCLGE_STATE_ROCE_REGISTERED,
	HCLGE_STATE_SERVICE_INITED,
	HCLGE_STATE_SERVICE_SCHED,
	HCLGE_STATE_RST_SERVICE_SCHED,
	HCLGE_STATE_RST_HANDLING,
	HCLGE_STATE_MBX_SERVICE_SCHED,
	HCLGE_STATE_MBX_HANDLING,
	HCLGE_STATE_STATISTICS_UPDATING,
	HCLGE_STATE_CMD_DISABLE,
	HCLGE_STATE_MAX
};

enum hclge_evt_cause {
	HCLGE_VECTOR0_EVENT_RST,
	HCLGE_VECTOR0_EVENT_MBX,
	HCLGE_VECTOR0_EVENT_ERR,
	HCLGE_VECTOR0_EVENT_OTHER,
};

#define HCLGE_MPF_ENBALE 1

enum HCLGE_MAC_SPEED {
	HCLGE_MAC_SPEED_UNKNOWN = 0,		/* unknown */
	HCLGE_MAC_SPEED_10M	= 10,		/* 10 Mbps */
	HCLGE_MAC_SPEED_100M	= 100,		/* 100 Mbps */
	HCLGE_MAC_SPEED_1G	= 1000,		/* 1000 Mbps   = 1 Gbps */
	HCLGE_MAC_SPEED_10G	= 10000,	/* 10000 Mbps  = 10 Gbps */
	HCLGE_MAC_SPEED_25G	= 25000,	/* 25000 Mbps  = 25 Gbps */
	HCLGE_MAC_SPEED_40G	= 40000,	/* 40000 Mbps  = 40 Gbps */
	HCLGE_MAC_SPEED_50G	= 50000,	/* 50000 Mbps  = 50 Gbps */
	HCLGE_MAC_SPEED_100G	= 100000	/* 100000 Mbps = 100 Gbps */
};

enum HCLGE_MAC_DUPLEX {
	HCLGE_MAC_HALF,
	HCLGE_MAC_FULL
};

#define QUERY_SFP_SPEED		0
#define QUERY_ACTIVE_SPEED	1

struct hclge_mac {
	u8 phy_addr;
	u8 flag;
	u8 media_type;	/* port media type, e.g. fibre/copper/backplane */
	u8 mac_addr[ETH_ALEN];
	u8 autoneg;
	u8 duplex;
	u8 support_autoneg;
	u8 speed_type;	/* 0: sfp speed, 1: active speed */
	u32 speed;
	u32 speed_ability; /* speed ability supported by current media */
	u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
	u32 fec_mode; /* active fec mode */
	u32 user_fec_mode;
	u32 fec_ability;
	int link;	/* store the link status of mac & phy (if phy exit) */
	struct phy_device *phydev;
	struct mii_bus *mdio_bus;
	phy_interface_t phy_if;
	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
};

struct hclge_hw {
	void __iomem *io_base;
	struct hclge_mac mac;
	int num_vec;
	struct hclge_cmq cmq;
};

/* TQP stats */
struct hlcge_tqp_stats {
	/* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
	/* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
};

struct hclge_tqp {
	/* copy of device pointer from pci_dev,
	 * used when perform DMA mapping
	 */
	struct device *dev;
	struct hnae3_queue q;<