/* * flexcan.c - FLEXCAN CAN controller driver * * Copyright (c) 2005-2006 Varma Electronics Oy * Copyright (c) 2009 Sascha Hauer, Pengutronix * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> * Copyright (c) 2014 David Jander, Protonic Holland * * Based on code originally by Andrey Volkov <avolkov@varma-el.com> * * LICENCE: * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * */#include<linux/netdevice.h>#include<linux/can.h>#include<linux/can/dev.h>#include<linux/can/error.h>#include<linux/can/led.h>#include<linux/can/rx-offload.h>#include<linux/clk.h>#include<linux/delay.h>#include<linux/interrupt.h>#include<linux/io.h>#include<linux/module.h>#include<linux/of.h>#include<linux/of_device.h>#include<linux/platform_device.h>#include<linux/regulator/consumer.h>#define DRV_NAME "flexcan"/* 8 for RX fifo and 2 error handling */#define FLEXCAN_NAPI_WEIGHT (8 + 2)/* FLEXCAN module configuration register (CANMCR) bits */#define FLEXCAN_MCR_MDIS BIT(31)#define FLEXCAN_MCR_FRZ BIT(30)#define FLEXCAN_MCR_FEN BIT(29)#define FLEXCAN_MCR_HALT BIT(28)#define FLEXCAN_MCR_NOT_RDY BIT(27)#define FLEXCAN_MCR_WAK_MSK BIT(26)#define FLEXCAN_MCR_SOFTRST BIT(25)#define FLEXCAN_MCR_FRZ_ACK BIT(24)#define FLEXCAN_MCR_SUPV BIT(23)#define FLEXCAN_MCR_SLF_WAK BIT(22)#define FLEXCAN_MCR_WRN_EN BIT(21)#define FLEXCAN_MCR_LPM_ACK BIT(20)#define FLEXCAN_MCR_WAK_SRC BIT(19)#define FLEXCAN_MCR_DOZE BIT(18)#define FLEXCAN_MCR_SRX_DIS BIT(17)#define FLEXCAN_MCR_IRMQ BIT(16)#define FLEXCAN_MCR_LPRIO_EN BIT(13)#define FLEXCAN_MCR_AEN BIT(12)/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)#define FLEXCAN_MCR_IDAM_A (0x0 << 8)#define FLEXCAN_MCR_IDAM_B (0x1 << 8)#define FLEXCAN_MCR_IDAM_C (0x2 << 8)#define FLEXCAN_MCR_IDAM_D (0x3 << 8)/* FLEXCAN control register (CANCTRL) bits */#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)#define FLEXCAN_CTRL_BOFF_MSK BIT(15)#define FLEXCAN_CTRL_ERR_MSK BIT(14)#define FLEXCAN_CTRL_CLK_SRC BIT(13)#define FLEXCAN_CTRL_LPB BIT(12)#define FLEXCAN_CTRL_TWRN_MSK BIT(11)#define FLEXCAN_CTRL_RWRN_MSK BIT(10)#define FLEXCAN_CTRL_SMP BIT(7)#define FLEXCAN_CTRL_BOFF_REC BIT(6)#define FLEXCAN_CTRL_TSYN BIT(5)#define FLEXCAN_CTRL_LBUF BIT(4)#define FLEXCAN_CTRL_LOM BIT(3)#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)#define FLEXCAN_CTRL_ERR_STATE \ (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ FLEXCAN_CTRL_BOF