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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller
*
* Copyright (C) 2015 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/timer.h>
#include <linux/types.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/slot-gpio.h>
#define MESON_MX_SDIO_ARGU 0x00
#define MESON_MX_SDIO_SEND 0x04
#define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0)
#define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8)
#define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16)
#define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17)
#define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18)
#define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19)
#define MESON_MX_SDIO_SEND_DATA BIT(20)
#define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21)
#define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24)
#define MESON_MX_SDIO_CONF 0x08
#define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0
#define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10
#define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10)
#define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11)
#define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12)
#define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18)
#define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19)
#define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20)
#define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21)
#define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23)
#define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29)
#define MESON_MX_SDIO_IRQS 0x0c
#define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0)
#define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4)
#define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5)
#define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6)
#define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7)
#define MESON_MX_SDIO_IRQS_IF_INT BIT(8)
#define MESON_MX_SDIO_IRQS_CMD_INT BIT(9)
#define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12)
#define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16)
#define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17)
#define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18)
#define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19)
#define MESON_MX_SDIO_IRQC 0x10
#define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3)
#define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4)
#define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6)
#define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8)
#define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9)
#define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10)
#define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15)
#define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30)
#define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31)
#define MESON_MX_SDIO_MULT 0x14
#define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0)
#define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2)
#define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3)
#define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4)
#define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5)
#define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8)
#define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10)
#define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11)
#define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12)
#define MESON_MX_SDIO_ADDR 0x18
#define MESON_MX_SDIO_EXT 0x1c
#define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16)
#define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024)
#define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1)
#define MESON_MX_SDIO_MAX_SLOTS 3
struct meson_mx_mmc_host {
struct device *controller_dev;
struct clk *parent_clk;
struct clk *core_clk;
struct clk_divider cfg_div;
struct clk *cfg_div_clk;
struct clk_fixed_factor fixed_factor;
struct clk *fixed_factor_clk;
void __iomem *base;
int irq;
spinlock_t irq_lock;
struct timer_list cmd_timeout;
unsigned int slot_id;
struct mmc_host *mmc;
struct mmc_request *mrq;
struct mmc_command *cmd;
int error;
};
static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask,
u32 val)
{
struct meson_mx_mmc_host *host = mmc_priv(mmc);
u32 regval;
regval = readl(host->base + reg);
regval &= ~mask;
regval |= (val & mask);
writel(regval, host->base + reg);
}
static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host)
{
writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC);
udelay(2);
}
static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd)
{
if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
return cmd->mrq->cmd;
else if (mmc_op_multi(cmd->opcode) &&
(!cmd->mrq->sbc || cmd->error || cmd->data->error))
return cmd->mrq->stop;
else
return NULL;
}
static void meson_mx_mmc_start_cmd(struct mmc_host *mmc,
struct mmc_command *cmd)
{
struct meson_mx_mmc_host *host = mmc_priv(mmc);
unsigned int pack_size;
unsigned long irqflags, timeout;
u32 mult, send = 0, ext = 0;
host->cmd = cmd;
if (cmd->busy_timeout)
timeout = msecs_to_jiffies(cmd->busy_timeout);
else
timeout = msecs_to_jiffies(1000);
switch (mmc_resp_type(cmd)) {
case MMC_RSP_R1:
case MMC_RSP_R1B:
case MMC_RSP_R3:
/* 7 (CMD) + 32 (response) + 7 (CRC) -1 */
send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45);
break;
case MMC_RSP_R2:
/* 7 (CMD) + 120 (response) + 7 (CRC) -1 */
send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133);
send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8;
break;
default:
break;
}
if (!(cmd->flags & MMC_RSP_CRC))
send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7;
if (cmd->flags & MMC_RSP_BUSY)
send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY;
if (cmd->data) {
send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
(cmd->data->blocks - 1));
pack_size = cmd->data->blksz * BITS_PER_BYTE;
if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4;
else
pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1;
ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
pack_size);
if (cmd->data->flags & MMC_DATA_WRITE)
send |= MESON_MX_SDIO_SEND_DATA;
else
send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA;
cmd->data->bytes_xfered = 0;
}
send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK,
(0x40 | cmd->opcode));
spin_lock_irqsave(&host->irq_lock, irqflags);
mult = readl(host->base + MESON_MX_SDIO_MULT);
mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK;
mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id);
mult |= BIT(31);
writel(mult, host->base + MESON_MX_SDIO_MULT);
/* enable the CMD done interrupt */
meson_mx_mmc_mask_bits
|