path: root/drivers/media/pci/cx88/cx88-reg.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * cx88x-hw.h - CX2388x register offsets
 *
 * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
 *		  2001 Michael Eskin
 *		  2002 Yurij Sysoev <yurij@naturesoft.net>
 *		  2003 Gerd Knorr <kraxel@bytesex.org>
 */

#ifndef _CX88_REG_H_
#define _CX88_REG_H_

/*
 * PCI IDs and config space
 */

#ifndef PCI_VENDOR_ID_CONEXANT
# define PCI_VENDOR_ID_CONEXANT		0x14F1
#endif
#ifndef PCI_DEVICE_ID_CX2300_VID
# define PCI_DEVICE_ID_CX2300_VID	0x8800
#endif

#define CX88X_DEVCTRL 0x40
#define CX88X_EN_TBFX 0x02
#define CX88X_EN_VSFX 0x04

/*
 * PCI controller registers
 */

/* Command and Status Register */
#define F0_CMD_STAT_MM      0x2f0004
#define F1_CMD_STAT_MM      0x2f0104
#define F2_CMD_STAT_MM      0x2f0204
#define F3_CMD_STAT_MM      0x2f0304
#define F4_CMD_STAT_MM      0x2f0404

/* Device Control #1 */
#define F0_DEV_CNTRL1_MM    0x2f0040
#define F1_DEV_CNTRL1_MM    0x2f0140
#define F2_DEV_CNTRL1_MM    0x2f0240
#define F3_DEV_CNTRL1_MM    0x2f0340
#define F4_DEV_CNTRL1_MM    0x2f0440

/* Device Control #1 */
#define F0_BAR0_MM          0x2f0010
#define F1_BAR0_MM          0x2f0110
#define F2_BAR0_MM          0x2f0210
#define F3_BAR0_MM          0x2f0310
#define F4_BAR0_MM          0x2f0410

/*
 * DMA Controller registers
 */

#define MO_PDMA_STHRSH      0x200000 // Source threshold
#define MO_PDMA_STADRS      0x200004 // Source target address
#define MO_PDMA_SIADRS      0x200008 // Source internal address
#define MO_PDMA_SCNTRL      0x20000C // Source control
#define MO_PDMA_DTHRSH      0x200010 // Destination threshold
#define MO_PDMA_DTADRS      0x200014 // Destination target address
#define MO_PDMA_DIADRS      0x200018 // Destination internal address
#define MO_PDMA_DCNTRL      0x20001C // Destination control
#define MO_LD_SSID          0x200030 // Load subsystem ID
#define MO_DEV_CNTRL2       0x200034 // Device control
#define MO_PCI_INTMSK       0x200040 // PCI interrupt mask
#define MO_PCI_INTSTAT      0x200044 // PCI interrupt status
#define MO_PCI_INTMSTAT     0x200048 // PCI interrupt masked status
#define MO_VID_INTMSK       0x200050 // Video interrupt mask
#define MO_VID_INTSTAT      0x200054 // Video interrupt status
#define MO_VID_INTMSTAT     0x200058 // Video interrupt masked status
#define MO_VID_INTSSTAT     0x20005C // Video interrupt set status
#define MO_AUD_INTMSK       0x200060 // Audio interrupt mask
#define MO_AUD_INTSTAT      0x200064 // Audio interrupt status
#define MO_AUD_INTMSTAT     0x200068 // Audio interrupt masked status
#define MO_AUD_INTSSTAT     0x20006C // Audio interrupt set status
#define MO_TS_INTMSK        0x200070 // Transport stream interrupt mask
#define MO_TS_INTSTAT       0x200074 // Transport stream interrupt status
#define MO_TS_INTMSTAT      0x200078 // Transport stream interrupt mask status
#define MO_TS_INTSSTAT      0x20007C // Transport stream interrupt set status
#define MO_VIP_INTMSK       0x200080 // VIP interrupt mask
#define MO_VIP_INTSTAT      0x200084 // VIP interrupt status
#define MO_VIP_INTMSTAT     0x200088 // VIP interrupt masked status
#define MO_VIP_INTSSTAT     0x20008C // VIP interrupt set status
#define MO_GPHST_INTMSK     0x200090 // Host interrupt mask
#define MO_GPHST_INTSTAT    0x200094 // Host interrupt status
#define MO_GPHST_INTMSTAT   0x200098 // Host interrupt masked status
#define MO_GPHST_INTSSTAT   0x20009C // Host interrupt set status

// DMA Channels 1-6 belong to SPIPE
#define MO_DMA7_PTR1        0x300018 // {24}RW* DMA Current Ptr : Ch#7
#define MO_DMA8_PTR1        0x30001C // {24}RW* DMA Current Ptr : Ch#8

// DMA Channels 9-20 belong to SPIPE
#define MO_DMA21_PTR1       0x300080 // {24}R0* DMA Current Ptr : Ch#21
#define MO_DMA22_PTR1       0x300084 // {24}R0* DMA Current Ptr : Ch#22
#define MO_DMA23_PTR1       0x300088 // {24}R0* DMA Current Ptr : Ch#23
#define MO_DMA24_PTR1       0x30008C // {24}R0* DMA Current Ptr : Ch#24
#define MO_DMA25_PTR1       0x300090 // {24}R0* DMA Current Ptr : Ch#25
#define MO_DMA26_PTR1       0x300094 // {24}R0* DMA Current Ptr : Ch#26
#define MO_DMA27_PTR1       0x300098 // {24}R0* DMA Current Ptr : Ch#27
#define MO_DMA28_PTR1       0x30009C // {24}R0* DMA Current Ptr : Ch#28
#define MO_DMA29_PTR1       0x3000A0 // {24}R0* DMA Current Ptr : Ch#29
#define MO_DMA30_PTR1       0x3000A4 // {24}R0* DMA Current Ptr : Ch#30
#define MO_DMA31_PTR1       0x3000A8 // {24}R0* DMA Current Ptr : Ch#31
#define MO_DMA32_PTR1       0x3000AC // {24}R0* DMA Current Ptr : Ch#32

#define MO_DMA21_PTR2       0x3000C0 // {24}RW* DMA Tab Ptr : Ch#21
#define MO_DMA22_PTR2       0x3000C4 // {24}RW* DMA Tab Ptr : Ch#22
#define MO_DMA23_PTR2       0x3000C8 // {24}RW* DMA Tab Ptr : Ch#23
#define MO_DMA24_PTR2       0x3000CC // {24}RW* DMA Tab Ptr : Ch#24
#define MO_DMA25_PTR2       0x3000D0 // {24}RW* DMA Tab Ptr : Ch#25
#define MO_DMA26_PTR2       0x3000D4 // {24}RW* DMA Tab Ptr : Ch#26
#define MO_DMA27_PTR2       0x3000D8 // {24}RW* DMA Tab Ptr : Ch#27
#define MO_DMA28_PTR2       0x3000DC // {24}RW* DMA Tab Ptr : Ch#28
#define MO_DMA29_PTR2       0x3000E0 // {24}RW* DMA Tab Ptr : Ch#29
#define MO_DMA30_PTR2       0x3000E4 // {24}RW* DMA Tab Ptr : Ch#30
#define MO_DMA31_PTR2       0x3000E8 // {24}RW* DMA Tab Ptr : Ch#31
#define MO_DMA32_PTR2       0x3000EC // {24}RW* DMA Tab Ptr : Ch#32

#define MO_DMA21_CNT1       0x300100 // {11}RW* DMA Buffer Size : Ch#21
#define MO_DMA22_CNT1       0x300104 // {11}RW* DMA Buffer Size : Ch#22
#define MO_DMA23_CNT1       0x300108 // {11}RW* DMA Buffer Size : Ch#23
#define MO_DMA24_CNT1       0x30010C // {11}RW* DMA Buffer Size : Ch#24
#define MO_DMA25_CNT1       0x300110 // {11}RW* DMA Buffer Size : Ch#25
#define MO_DMA26_CNT1       0x300114 // {11}RW* DMA Buffer Size : Ch#26
#define MO_DMA27_CNT1       0x300118 // {11}RW* DMA Buffer Size : Ch#27
#define MO_DMA28_CNT1       0x30011C // {11}RW* DMA Buffer Size : Ch#28
#define MO_DMA29_CNT1       0x300120 // {11}RW* DMA Buffer Size : Ch#29
#define MO_DMA30_CNT1       0x300124 // {11}RW* DMA Buffer Size : Ch#30
#define MO_DMA31_CNT1       0x300128 // {11}RW* DMA Buffer Size : Ch#31
#define MO_DMA32_CNT1       0x30012C // {11}RW* DMA Buffer Size : Ch#32

#define MO_DMA21_CNT2       0x300140 // {11}RW* DMA Table Size : Ch#21
#define MO_DMA22_CNT2       0x300144 // {11}RW* DMA Table Size : Ch#22
#define MO_DMA23_CNT2       0x300148 // {11}RW* DMA Table Size : Ch#23
#define MO_DMA24_CNT2       0x30014C // {11}RW* DMA Table Size : Ch#24
#define MO_DMA25_CNT2       0x300150 // {11}RW* DMA Table Size : Ch#25
#define MO_DMA26_CNT2       0x300154 // {11}RW* DMA Table Size : Ch#26
#define MO_DMA27_CNT2       0x300158 // {11}RW* DMA Table Size : Ch#27
#define MO_DMA28_CNT2       0x30015C // {11}RW* DMA Table Size : Ch#28
#define MO_DMA29_CNT2       0x300160 // {11}RW* DMA Table Size : Ch#29
#define MO_DMA30_CNT2       0x300164 // {11}RW* DMA Table Size : Ch#30
#define MO_DMA31_CNT2       0x300168 // {11}RW* DMA Table Size : Ch#31
#define MO_DMA32_CNT2       0x30016C // {11}RW* DMA Table Size : Ch#32

/*
 * Video registers
 */

#define MO_VIDY_DMA         0x310000 // {64}RWp Video Y
#define MO_VIDU_DMA         0x310008 // {64}RWp Video U
#define MO_VIDV_DMA         0x310010 // {64}RWp Video V
#define MO_VBI_DMA          0x310018 // {64}RWp VBI (Vertical blanking interval)

#define MO_DEVICE_STATUS    0x310100
#define MO_INPUT_FORMAT     0x310104
#define MO_AGC_BURST        0x31010c
#define MO_CONTR_BRIGHT     0x310110
#define MO_UV_SATURATION    0x310114
#define MO_HUE              0x310118
#define MO_HTOTAL           0x310120
#define MO_HDELAY_EVEN      0x310124
#define MO_HDELAY_ODD       0x310128
#define MO_VDELAY_ODD       0x31012c
#define MO_VDELAY_EVEN      0x310130
#define MO_HACTIVE_EVEN     0x31013c
#define MO_HACTIVE_ODD      0x310140
#define MO_VACTIVE_EVEN     0x310144
#define MO_VACTIVE_ODD      0x310148
#define MO_HSCALE_EVEN      0x31014c
#define MO_HSCALE_ODD       0x310150
#define MO_VSCALE_EVEN      0x310154
#define MO_FILTER_EVEN      0x31015c
#define MO_VSCALE_ODD       0x310158
#define MO_FILTER_ODD       0x310160
#define MO_OUTPUT_FORMAT    0x310164

#define MO_PLL_REG          0x310168 // PLL register
#define MO_PLL_ADJ_CTRL     0x31016c // PLL adjust control register
#define MO_SCONV_REG        0x310170 // sample rate conversion register
#define MO_SCONV_FIFO       0x310174 // sample rate conversion fifo
#define MO_SUB_STEP         0x310178 // subcarrier step size
#define MO_SUB_STEP_DR      0x31017c // subcarrier step size for DR line

#define MO_CAPTURE_CTRL     0x310180 // capture control
#define MO_COLOR_CTRL       0x310184
#define MO_VBI_PACKET       0x310188 // vbi packet size / delay
#define MO_FIELD_COUNT      0x310190 // field counter
#define MO_VIP_CONFIG       0x310194
#define MO_VBOS_CONTROL	    0x3101a8

#define MO_AGC_BACK_VBI     0x310200
#define MO_AGC_SYNC_TIP1    0x310208

#define MO_VIDY_GPCNT       0x31C020 // {16}RO Video Y general purpose counter
#define MO_VIDU_GPCNT       0x31C024 // {16}RO Video U general purpose counter
#define MO_VIDV_GPCNT       0x31C028 // {16}RO Video V general purpose counter
#define MO_VBI_GPCNT        0x31C02C // {16}RO VBI general purpose counter
#define MO_VIDY_GPCNTRL     0x31C030 // {2}WO Video Y general purpose control
#define MO_VIDU_GPCNTRL     0x31C034 // {2}WO Video U general purpose control
#define MO_VIDV_GPCNTRL     0x31C038 // {2}WO Video V general purpose control
#define MO_VBI_GPCNTRL      0x31C03C // {2}WO VBI general purpose counter
#define MO_VID_DMACNTRL     0x31C040 // {8}RW Video DMA control
#define MO_VID_XFR_STAT     0x31C044 // {1}RO Video transfer status

/*
 * audio registers
 */

#define MO_AUDD_DMA         0x320000 // {64}RWp Audio downstream
#define MO_AUDU_DMA         0x320008 // {64}RWp Audio upstream
#define MO_AUDR_DMA         0x320010 // {64}RWp Audio RDS (downstream)
#define MO_AUDD_GPCNT       0x32C020 // {16}RO Audio down general purpose counter
#define MO_AUDU_GPCNT       0x32C024 // {16}RO Audio up general purpose counter
#define MO_AUDR_GPCNT       0x32C028 // {16}RO Audio RDS general purpose counter
#define MO_AUDD_GPCNTRL     0x32C030 // {2}WO Audio down general purpose control
#define MO_AUDU_GPCNTRL     0x32C034 // {2}WO Audio up general purpose control
#define MO_AUDR_GPCNTRL     0x32C038 // {2}WO Audio RDS general purpose control
#define MO_AUD_DMACNTRL     0x32C040 // {6}RW Audio DMA control
#define MO_AUD_XFR_STAT     0x32C044 // {1}RO Audio transfer status
#define MO_AUDD_LNGTH       0x32C048 // {12}RW Audio down line length
#define MO_AUDR_LNGTH       0x32C04C // {12}RW Audio RDS line length

#define AUD_INIT                 0x320100
#define AUD_INIT_LD              0x320104
#define AUD_SOFT_RESET           0x320108
#define AUD_I2SINPUTCNTL         0x320120
#define AUD_BAUDRATE             0x320124
#define AUD_I2SOUTPUTCNTL        0x320128
#define AAGC_HYST                0x320134
#define AAGC_GAIN                0x320138
#define AAGC_DEF                 0x32013c
#define AUD_IIR1_0_SEL           0x320150
#define AUD_IIR1_0_SHIFT         0x320154
#define AUD_IIR1_1_SEL           0x320158
#define AUD_IIR1_1_SHIFT         0x32015c
#define AUD_IIR1_2_SEL           0x320160
#define AUD_IIR1_2_SHIFT         0x320164
#define AUD_IIR1_3_SEL           0x320168
#define AUD_IIR1_3_SHIFT         0x32016c
#define AUD_IIR1_4_SEL           0x320170
#define AUD_IIR1_4_SHIFT         0x32017c
#define AUD_IIR1_5_SEL           0x320180
#define AUD_IIR1_5_SHIFT         0x320184
#define AUD_IIR2_0_SEL           0x320190
#define AUD_IIR2_0_SHIFT         0x320194
#define AUD_IIR2_1_SEL           0x320198
#define AUD_IIR2_1_SHIFT         0x32019c
#define AUD_IIR2_2_SEL           0x3201a0
#define AUD_IIR2_2_SHIFT         0x3201a4
#define AUD_IIR2_3_SEL           0x3201a8
#define AUD_IIR2_3_SHIFT         0x3201ac
#define AUD_IIR3_0_SEL           0x3201c0
#define AUD_IIR3_0_SHIFT         0x3201c4
#define AUD_IIR3_1_SEL           0x3201c8
#define AUD_IIR3_1_SHIFT         0x3201cc
#define AUD_IIR3_2_SEL           0x3201d0
#define AUD_IIR3_2_SHIFT         0x3201d4
#define AUD_IIR4_0_SEL           0x3201e0
#define AUD_IIR4_0_SHIFT         0x3201e4
#define AUD_IIR4_1_SEL           0x3201e8
#define AUD_IIR4_1_SHIFT         0x3201ec
#define AUD_IIR4_2_SEL           0x3201f0
#define AUD_IIR4_2_SHIFT         0x3201f4
#define AUD_IIR4_0_CA0           0x320200
#define AUD_IIR4_0_CA1           0x320204
#define AUD_IIR4_0_CA2           0x320208
#define AUD_IIR4_0_CB0           0x32020c
#define AUD_IIR4_0_CB1           0x320210
#define AUD_IIR4_1_CA0           0x320214
#define AUD_IIR4_1_CA1           0x320218
#define AUD_IIR4_1_CA2           0x32021c
#define AUD_IIR4_1_CB0           0x320220
#define AUD_IIR4_1_CB1           0x320224
#define AUD_IIR4_2_CA0           0x320228
#define AUD_IIR4_2_CA1           0x32022c
#define AUD_IIR4_2_CA2           0x320230
#define AUD_IIR4_2_CB0           0x320234
#define AUD_IIR4_2_CB1           0x320238
#define AUD_HP_MD_IIR4_1         0x320250
#define AUD_HP_PROG_IIR4_1       0x320254
#define AUD_FM_MODE_ENABLE       0x320258
#define AUD_POLY0_DDS_CONSTANT   0x320270
#define AUD_DN0_FREQ             0x320274
#define AUD_DN1_FREQ             0x320278
#define AUD_DN1_FREQ_SHIFT       0x32027c
#define AUD_DN1_AFC              0x320280
#define AUD_DN1_SRC_SEL          0x320284
#define AUD_DN1_SHFT             0x320288
#define AUD_DN2_FREQ             0x32028c
#define AUD_DN2_FREQ_SHIFT       0x320290
#define AUD_DN2_AFC              0x320294
#define AUD_DN2_SRC_SEL          0x320298
#define AUD_DN2_SHFT             0x32029c
#define AUD_CRDC0_SRC_SEL        0x320300
#define AUD_CRDC0_SHIFT          0x320304
#define AUD_CORDIC_SHIFT_0       0x320308
#define AUD_CRDC1_SRC_SEL        0x32030c
#define AUD_CRDC1_SHIFT          0x320310
#define AUD_CORDIC_SHIFT_1       0x320314
#define AUD_DCOC_0_SRC           0x320320
#define AUD_DCOC0_SHIFT          0x320324
#define AUD_DCOC_0_SHIFT_IN0     0x320328
#define AUD_DCOC_0_SHIFT_IN1     0x32032c
#define AUD_DCOC_1_SRC           0x320330
#define AUD_DCOC1_SHIFT          0x320334
#define AUD_DCOC_1_SHIFT_IN0     0x320338
#define AUD_DCOC_1_SHIFT_IN1     0x32033c
#define AUD_DCOC_2_SRC           0x320340
#define AUD_DCOC2_SHIFT          0x320344
#define AUD_DCOC_2_SHIFT_IN0     0x320348
#define AUD_DCOC_2_SHIFT_IN1     0x32034c
#define AUD_DCOC_PASS_IN         0x320350
#define AUD_PDET_SRC             0x320370
#define AUD_PDET_SHIFT           0x320374
#define AUD_PILOT_BQD_1_K0       0x320380
#define AUD_PILOT_BQD_1_K1       0x320384
#define AUD_PILOT_BQD_1_K2       0x320388
#define AUD_PILOT_BQD_1_K3       0x32038c
#define AUD_PILOT_BQD_1_K4       0x320390
#define AUD_PILOT_BQD_2_K0       0x320394
#define AUD_PILOT_BQD_2_K1       0x320398
#define AUD_PILOT_BQD_2_K2       0x32039c
#define AUD_PILOT_BQD_2_K3       0x3203a0
#define AUD_PILOT_BQD_2_K4       0x3203a4
#define AUD_THR_FR               0x3203c0
#define AUD_X_PROG               0x3203c4
#define AUD_Y_PROG               0x3203c8
#define AUD_HARMONIC_MULT        0x3203cc
#define AUD_C1_UP_THR            0x3203d0
#define AUD_C1_LO_THR            0x3203d4
#define AUD_C2_UP_THR            0x3203d8
#define AUD_C2_LO_THR            0x3203dc
#define AUD_PLL_EN               0x320400
#define AUD_PLL_SRC              0x320404
#define AUD_PLL_SHIFT            0x320408
#define AUD_PLL_IF_SEL           0x32040c
#define AUD_PLL_IF_SHIFT         0x320410
#define AUD_BIQUAD_PLL_K0        0x320414
#define AUD_BIQUAD_PLL_K1        0x320418
#define AUD_BIQUAD_PLL_K2        0x32041c
#define AUD_BIQUAD_PLL_K3        0x320420
#define AUD_BIQUAD_PLL_K4        0x320424
#define AUD_DEEMPH0_SRC_SEL      0x320440
#define AUD_DEEMPH0_SHIFT        0x320444
#define AUD_DEEMPH0_G0           0x320448
#define AUD_DEEMPH0_A0           0x32044c
#define AUD_DEEMPH0_B0           0x320450
#define AUD_DEEMPH0_A1           0x320454
#define AUD_DEEMPH0_B1           0x320458
#define AUD_DEEMPH1_SRC_SEL      0x32045c
#define AUD_DEEMPH1_SHIFT        0x320460
#define AUD_DEEMPH1_G0           0x320464
#define AUD_DEEMPH1_A0           0x320468
#define AUD_DEEMPH1_B0           0x32046c
#define AUD_DEEMPH1_A1           0x320470
#define AUD_DEEMPH1_B1           0x320474
#define AUD_OUT0_SEL             0x320490
#define AUD_OUT0_SHIFT           0x320494
#define AUD_OUT1_SEL             0x320498
#define AUD_OUT1_SHIFT           0x32049c
#define AUD_RDSI_SEL             0x3204a0
#define AUD_RDSI_SHIFT           0x3204a4
#define AUD_RDSQ_SEL             0x3204a8
#define AUD_RDSQ_SHIFT           0x3204ac
#define AUD_DBX_IN_GAIN          0x320500
#define AUD_DBX_WBE_GAIN         0x320504
#define AUD_DBX_SE_GAIN          0x320508
#define AUD_DBX_RMS_WBE          0x32050c
#define AUD_DBX_RMS_SE           0x320510
#define AUD_DBX_SE_BYPASS        0x320514
#define AUD_FAWDETCTL            0x320530
#define AUD_FAWDETWINCTL         0x320534
#define AUD_DEEMPHGAIN_R         0x320538
#define AUD_DEEMPHNUMER1_R       0x32053c
#define AUD_DEEMPHNUMER2_R       0x320540
#define AUD_DEEMPHDENOM1_R       0x320544
#define AUD_DEEMPHDENOM2_R       0x320548
#define AUD_ERRLOGPERIOD_R       0x32054c
#define A