/* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_DPP_DCN10_H__
#define __DAL_DPP_DCN10_H__
#include "dpp.h"
#define TO_DCN10_DPP(dpp)\
container_of(dpp, struct dcn10_dpp, base)
/* TODO: Use correct number of taps. Using polaris values for now */
#define LB_TOTAL_NUMBER_OF_ENTRIES 5124
#define LB_BITS_PER_ENTRY 144
#define TF_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
//Used to resolve corner case
#define TF2_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## _ ## field_name ## post_fix
#define TF_REG_LIST_DCN(id) \
SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
SRI(OTG_H_BLANK, DSCL, id), \
SRI(OTG_V_BLANK, DSCL, id), \
SRI(SCL_MODE, DSCL, id), \
SRI(LB_DATA_FORMAT, DSCL, id), \
SRI(LB_MEMORY_CTRL, DSCL, id), \
SRI(DSCL_AUTOCAL, DSCL, id), \
SRI(SCL_BLACK_OFFSET, DSCL, id), \
SRI(DSCL_CONTROL, DSCL, id), \
SRI(SCL_TAP_CONTROL, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
SRI(DSCL_2TAP_CONTROL, DSCL, id), \
SRI(MPC_SIZE, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
SRI(RECOUT_START, DSCL, id), \
SRI(RECOUT_SIZE, DSCL, id), \
SRI(OBUF_CONTROL, DSCL, id), \
SRI(CM_ICSC_CONTROL, CM, id), \
SRI(CM_ICSC_C11_C12, CM, id), \
SRI(CM_ICSC_C33_C34, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI(CM_DGAM_LUT_INDEX, CM, id), \
SRI(CM_DGAM_LUT_DATA, CM, id), \
SRI(CM_CONTROL, CM, id), \
SRI(CM_DGAM_CONTROL, CM, id), \
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
SRI(CURSOR0_COLOR1, CNVC_CUR, id)
#define TF_REG_LIST_DCN10(id) \
TF_REG_LIST_DCN(id), \
SRI(CM_COMA_C11_C12, CM, id),\
SRI(CM_COMA_C33_C34, CM, id),\
SRI(CM_COMB_C11_C