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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver For Marvell Two-channel DMA Engine
*
* Copyright: Marvell International Ltd.
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/dmaengine.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/platform_data/dma-mmp_tdma.h>
#include <linux/of_device.h>
#include <linux/of_dma.h>
#include "dmaengine.h"
/*
* Two-Channel DMA registers
*/
#define TDBCR 0x00 /* Byte Count */
#define TDSAR 0x10 /* Src Addr */
#define TDDAR 0x20 /* Dst Addr */
#define TDNDPR 0x30 /* Next Desc */
#define TDCR 0x40 /* Control */
#define TDCP 0x60 /* Priority*/
#define TDCDPR 0x70 /* Current Desc */
#define TDIMR 0x80 /* Int Mask */
#define TDISR 0xa0 /* Int Status */
/* Two-Channel DMA Control Register */
#define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
#define TDCR_SSZ_12_BITS (0x1 << 22)
#define TDCR_SSZ_16_BITS (0x2 << 22)
#define TDCR_SSZ_20_BITS (0x3 << 22)
#define TDCR_SSZ_24_BITS (0x4 << 22)
#define TDCR_SSZ_32_BITS (0x5 << 22)
#define TDCR_SSZ_SHIFT (0x1 << 22)
#define TDCR_SSZ_MASK (0x7 << 22)
#define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
#define TDCR_ABR (0x1 << 20) /* Channel Abort */
#define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
#define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
#define TDCR_CHANACT (0x1 << 14) /* Channel Active */
#define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
#define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
#define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
#define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
#define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
#define TDCR_BURSTSZ_4B (0x0 << 6)
#define TDCR_BURSTSZ_8B (0x1 << 6)
#define TDCR_BURSTSZ_16B (0x3 << 6)
#define TDCR_BURSTSZ_32B (0x6 << 6)
#define TDCR_BURSTSZ_64B (0x7 << 6)
#define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
#define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
#define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
#define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
#define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
#define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
#define TDCR_BURSTSZ_128B (0x5 << 6)
#define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
#define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
#define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
#define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
#define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
#define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
#define TDCR_DSTDESCCONT (0x1 << 1)
#define TDCR_SRCDESTCONT (0x1 << 0)
/* Two-Channel DMA Int Mask Register */
#define TDIMR_COMP (0x1 << 0)
/* Two-Channel DMA Int Status Register */
#define TDISR_COMP (0x1 << 0)
/*
* Two-Channel DMA Descriptor Struct
* NOTE: desc's buf must be aligned to 16 bytes.
*/
struct mmp_tdma_desc {
u32 byte_cnt;
u32 src_addr;
u32 dst_addr;
u32 nxt_desc;
};
enum mmp_tdma_type {
MMP_AUD_TDMA = 0,
PXA910_SQU,
};
#define TDMA_MAX_XFER_BYTES SZ_64K
struct mmp_tdma_chan {
struct device *dev;
struct dma_chan chan;
struct dma_async_tx_descriptor desc;
struct tasklet_struct tasklet;
struct mmp_tdma_desc *desc_arr;
dma_addr_t desc_arr_phys;
int desc_num;
enum dma_transfer_direction dir;
dma_addr_t dev_addr;
u32 burst_sz;
enum dma_slave_buswidth buswidth;
enum dma_status status;
struct dma_slave_config slave_config;
int idx;
enum mmp_tdma_type type;
int irq;
void __iomem *reg_base;
size_t buf_len;
size_t period_len;
size_t pos;
struct gen_pool *pool;
};
#define TDMA_CHANNEL_NUM 2
struct mmp_tdma_device {
struct device *dev;
void __iomem *base;
struct dma_device device;
struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
};
#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
static int mmp_tdma_config_write(struct dma_chan *chan,
enum dma_transfer_direction dir,
struct dma_slave_config *dmaengine_cfg);
static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
{
writel(phys, tdmac->reg_base + TDNDPR);
writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
tdmac->reg_base + TDCR);
}
static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
{
if (enable)
writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
else
writel(0, tdmac->reg_base + TDIMR);
}
static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
{
/* enable dma chan */
writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
tdmac->reg_base + TDCR);
tdmac->status = DMA_IN_PROGRESS;
}
static int mmp_tdma_disable_chan(struct dma_chan *chan)
{
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
u32 tdcr;
tdcr = readl(tdmac->reg_base + TDCR);
tdcr |= TDCR_ABR;
tdcr &= ~TDCR_CHANEN;
writel(tdcr, tdmac->reg_base + TDCR);
tdmac->status = DMA_COMPLETE;
return 0;
}
static int mmp_tdma_resume_chan(struct dma_chan *chan)
{
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
tdmac->reg_base + TDCR);
tdmac->status = DMA_IN_PROGRESS;
return 0;
}
static int mmp_tdma_pause_chan(struct dma_chan *chan)
{
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
tdmac->reg_base + TDCR);
tdmac->status = DMA_PAUSED;
return 0;
}
static int mmp_tdma_config_chan(struct dma_chan *chan)
{
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
unsigned int tdcr = 0;
mmp_tdma_disable_chan(chan);
if (tdmac->dir == DMA_MEM_TO_DEV)
tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
else if (tdmac->dir == DMA_DEV_TO_MEM)
tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
if (tdmac->type == MMP_AUD_TDMA) {
tdcr |= TDCR_PACKMOD;
switch (tdmac->burst_sz) {
case 4:
tdcr |= TDCR_BURSTSZ_4B;
break;
case 8:
tdcr |= TDCR_BURSTSZ_8B;
break;
case 16:
tdcr |= TDCR_BURSTSZ_16B;
break;
case 32:
tdcr |= TDCR_BURSTSZ_32B;
break;
case 64:
tdcr |= TDCR_BURSTSZ_64B;
break;
case 128:
tdcr |= TDCR_BURSTSZ_128B;
break;
default:
dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
return -EINVAL;
}
switch (tdmac->buswidth) {
case DMA_SLAVE_BUSWIDTH_1_BYTE:
tdcr |= TDCR_SSZ_8_BITS;
break;
case DMA_SLAVE_BUSWIDTH_2_BYTES:
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