/*
* Freescale i.MX23/i.MX28 Data Co-Processor driver
*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/crypto.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/stmp_device.h>
#include <crypto/aes.h>
#include <crypto/sha.h>
#include <crypto/internal/hash.h>
#define DCP_MAX_CHANS 4
#define DCP_BUF_SZ PAGE_SIZE
#define DCP_ALIGNMENT 64
/* DCP DMA descriptor. */
struct dcp_dma_desc {
uint32_t next_cmd_addr;
uint32_t control0;
uint32_t control1;
uint32_t source;
uint32_t destination;
uint32_t size;
uint32_t payload;
uint32_t status;
};
/* Coherent aligned block for bounce buffering. */
struct dcp_coherent_block {
uint8_t aes_in_buf[DCP_BUF_SZ];
uint8_t aes_out_buf[DCP_BUF_SZ];
uint8_t sha_in_buf[DCP_BUF_SZ];
uint8_t aes_key[2 * AES_KEYSIZE_128];
struct dcp_dma_desc desc[DCP_MAX_CHANS];
};
struct dcp {
struct device *dev;
void __iomem *base;
uint32_t caps;
struct dcp_coherent_block *coh;
struct completion completion[DCP_MAX_CHANS];
struct mutex mutex[DCP_MAX_CHANS];
struct task_struct *thread[DCP_MAX_CHANS];
struct crypto_queue queue[DCP_MAX_CHANS];
};
enum dcp_chan {
DCP_CHAN_HASH_SHA = 0,
DCP_CHAN_CRYPTO = 2,
};
struct dcp_async_ctx {
/* Common context */
enum dcp_chan chan;
uint32_t fill;
/* SHA Hash-specific context */
struct mutex mutex;
uint32_t alg;
unsigned int hot:1;
/* Crypto-specific context */
struct crypto_ablkcipher *fallback;
unsigned int key_len;
uint8_t key[AES_KEYSIZE_128];
};
struct dcp_aes_req_ctx {
unsigned int enc:1;
unsigned int ecb:1;
};
struct dcp_sha_req_ctx {
unsigned int init:1;
unsigned int fini:1;
};
/*
* There can even be only one instance of the MXS DCP due to the
* design of Linux Crypto API.
*/
static struct dcp *global_sdcp;
/* DCP register layout. */
#define MXS_DCP_CTRL 0x00
#define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23)
#define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22)
#define MXS_DCP_STAT 0x10
#define MXS_DCP_STAT_CLR 0x18
#define MXS_DCP_STAT_IRQ_MASK 0xf
#define MXS_DCP_CHANNELCTRL 0x20
#define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
#define MXS_DCP_CAPABILITY1 0x40
#define MXS_DCP_CAPABILITY1_SHA256 (4 << 16)
#define MXS_DCP_CAPABILITY1_SHA1 (1 << 16)
#define MXS_DCP_CAPABILITY1_AES128 (1 << 0)
#define MXS_DCP_CONTEXT 0x50
#define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40))
#define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40))
#define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40))
#define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40))
/* DMA descriptor bits. */
#define MXS_DCP_CONTROL0_HASH_TERM (1 << 13)
#define MXS_DCP_CONTROL0_HASH_INIT (1 << 12)
#define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11)
#define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8)
#define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9)
#define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6)
#define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5)
#define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1)
#define MXS_DCP_CONTROL0_INTERRUPT (1 << 0)
#define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16)
#define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16)
#define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4)
#define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4)
#define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0)
static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
{
struct dcp *sdcp = global_sdcp;
const int chan = actx->chan;
uint32_t stat;
unsigned long ret;
struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
DMA_TO_DEVICE);
reinit_completion(&sdcp->completion[chan]);
/* Clear status register. */
writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
/* Load the DMA descriptor. */
writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
/* Increment the semaphore to start the DMA transfer. */
writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
ret = wait_for_completion_timeout(&sdcp->completion[chan],
msecs_to_jiffies(1000));
if (!ret) {
dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
chan,