/*
* rocket_int.h --- internal header file for rocket.c
*
* Written by Theodore Ts'o, Copyright 1997.
* Copyright 1997 Comtrol Corporation.
*
*/
/*
* Definition of the types in rcktpt_type
*/
#define ROCKET_TYPE_NORMAL 0
#define ROCKET_TYPE_MODEM 1
#define ROCKET_TYPE_MODEMII 2
#define ROCKET_TYPE_MODEMIII 3
#define ROCKET_TYPE_PC104 4
#include <linux/mutex.h>
#include <asm/io.h>
#include <asm/byteorder.h>
typedef unsigned char Byte_t;
typedef unsigned int ByteIO_t;
typedef unsigned int Word_t;
typedef unsigned int WordIO_t;
typedef unsigned long DWord_t;
typedef unsigned int DWordIO_t;
/*
* Note! Normally the Linux I/O macros already take care of
* byte-swapping the I/O instructions. However, all accesses using
* sOutDW aren't really 32-bit accesses, but should be handled in byte
* order. Hence the use of the cpu_to_le32() macro to byte-swap
* things to no-op the byte swapping done by the big-endian outl()
* instruction.
*/
#ifdef ROCKET_DEBUG_IO
static inline void sOutB(unsigned short port, unsigned char value)
{
#ifdef ROCKET_DEBUG_IO
printk("sOutB(%x, %x)...", port, value);
#endif
outb_p(value, port);
}
static inline void sOutW(unsigned short port, unsigned short value)
{
#ifdef ROCKET_DEBUG_IO
printk("sOutW(%x, %x)...", port, value);
#endif
outw_p(value, port);
}
static inline void sOutDW(unsigned short port, unsigned long value)
{
#ifdef ROCKET_DEBUG_IO
printk("sOutDW(%x, %lx)...", port, value);
#endif
outl_p(cpu_to_le32(value), port);
}
static inline unsigned char sInB(unsigned short port)
{
return inb_p(port);
}
static inline unsigned short sInW(unsigned short port)
{
return inw_p(port);
}
#else /* !ROCKET_DEBUG_IO */
#define sOutB(a, b) outb_p(b, a)
#define sOutW(a, b) outw_p(b, a)
#define sOutDW(port, value) outl_p(cpu_to_le32(value), port)
#define sInB(a) (inb_p(a))
#define sInW(a) (inw_p(a))
#endif /* ROCKET_DEBUG_IO */
/* This is used to move arrays of bytes so byte swapping isn't appropriate. */
#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
#define sInStrW(port, addr, count) if (count) insw(port, addr, count)
#define CTL_SIZE 8
#define AIOP_CTL_SIZE 4
#define CHAN_AIOP_SIZE 8
#define MAX_PORTS_PER_AIOP 8
#define MAX_AIOPS_PER_BOARD 4
#define MAX_PORTS_PER_BOARD 32
/* Bus type ID */
#define isISA 0
#define isPCI 1
#define isMC 2
/* Controller ID numbers */
#define CTLID_NULL -1 /* no controller exists */
#define CTLID_0001 0x0001 /* controller release 1 */
/* AIOP ID numbers, identifies AIOP type implementing channel */
#define AIOPID_NULL -1 /* no AIOP or channel exists */
#define AIOPID_0001 0x0001 /* AIOP release 1 */
#define NULLDEV -1 /* identifies non-existant device */
#define NULLCTL -1 /* identifies non-existant controller */
#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
#define NULLAIOP -1 /* identifies non-existant AIOP */
#define NULLCHAN -1 /* identifies non-existant channel */
/************************************************************************
Global Register Offsets - Direct Access - Fixed values
************************************************************************/
#define _CMD_REG 0x38 /* Command Register 8 Write */
#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
#define _UNUSED 0x3B /* Unused 8 */
#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
/************************************************************************
Channel Register Offsets for 1st channel in AIOP - Direct Access
************************************************************************/
#define _TD0 0x00 /* Transmit Data 16 Write */
#define _RD0 0x00 /* Receive Data 16 Read */
#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
/************************************************************************
Tx Control Register Offsets - Indexed - External - Fixed
************************************************************************/
#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
/************************************************************************
Memory Controller