1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
|
#ifndef __ALPHA_IO_H
#define __ALPHA_IO_H
#ifdef __KERNEL__
#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/compiler.h>
#include <asm/pgtable.h>
#include <asm/machvec.h>
#include <asm/hwrpb.h>
/* The generic header contains only prototypes. Including it ensures that
the implementation we have here matches that interface. */
#include <asm-generic/iomap.h>
/* We don't use IO slowdowns on the Alpha, but.. */
#define __SLOW_DOWN_IO do { } while (0)
#define SLOW_DOWN_IO do { } while (0)
/*
* Virtual -> physical identity mapping starts at this offset
*/
#ifdef USE_48_BIT_KSEG
#define IDENT_ADDR 0xffff800000000000UL
#else
#define IDENT_ADDR 0xfffffc0000000000UL
#endif
/*
* We try to avoid hae updates (thus the cache), but when we
* do need to update the hae, we need to do it atomically, so
* that any interrupts wouldn't get confused with the hae
* register not being up-to-date with respect to the hardware
* value.
*/
extern inline void __set_hae(unsigned long new_hae)
{
unsigned long flags = swpipl(IPL_MAX);
barrier();
alpha_mv.hae_cache = new_hae;
*alpha_mv.hae_register = new_hae;
mb();
/* Re-read to make sure it was written. */
new_hae = *alpha_mv.hae_register;
setipl(flags);
barrier();
}
extern inline void set_hae(unsigned long new_hae)
{
if (new_hae != alpha_mv.hae_cache)
__set_hae(new_hae);
}
/*
* Change virtual addresses to physical addresses and vv.
*/
#ifdef USE_48_BIT_KSEG
static inline unsigned long virt_to_phys(void *address)
{
return (unsigned long)address - IDENT_ADDR;
}
static inline void * phys_to_virt(unsigned long address)
{
return (void *) (address + IDENT_ADDR);
}
#else
static inline unsigned long virt_to_phys(void *address)
{
unsigned long phys = (unsigned long)address;
/* Sign-extend from bit 41. */
phys <<= (64 - 41);
phys = (long)phys >> (64 - 41);
/* Crop to the physical address width of the processor. */
phys &= (1ul << hwrpb->pa_bits) - 1;
return phys;
}
static inline void * phys_to_virt(unsigned long address)
{
return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1)));
}
#endif
#define page_to_phys(page) page_to_pa(page)
static inline dma_addr_t __deprecated isa_page_to_bus(struct page *page)
{
return page_to_phys(page);
}
/* Maximum PIO space address supported? */
#define IO_SPACE_LIMIT 0xffff
/*
* Change addresses as seen by the kernel (virtual) to addresses as
* seen by a device (bus), and vice versa.
*
* Note that this only works for a limited range of kernel addresses,
* and very well may not span all memory. Consider this interface
* deprecated in favour of the DMA-mapping API.
*/
extern unsigned long __direct_map_base;
extern unsigned long __direct_map_size;
static inline unsigned long __deprecated virt_to_bus(void *address)
{
unsigned long phys = virt_to_phys(address);
unsigned long bus = phys + __direct_map_base;
return phys <= __direct_map_size ? bus : 0;
}
#define isa_virt_to_bus virt_to_bus
static inline void * __deprecated bus_to_virt(unsigned long address)
{
void *virt;
/* This check is a sanity check but also ensures that bus address 0
maps to virtual address 0 which is useful to detect null pointers
(the NCR driver is much simpler if NULL pointers are preserved). */
address -= __direct_map_base;
virt = phys_to_virt(address);
return (long)address <= 0 ? NULL : virt;
}
#define isa_bus_to_virt bus_to_virt
/*
* There are different chipsets to interface the Alpha CPUs to the world.
*/
#define IO_CONCAT(a,b) _IO_CONCAT(a,b)
#define _IO_CONCAT(a,b) a ## _ ## b
#ifdef CONFIG_ALPHA_GENERIC
/* In a generic kernel, we always go through the machine vector. */
#define REMAP1(TYPE, NAME, QUAL) \
static inline TYPE generic_##NAME(QUAL void __iomem *addr) \
{ \
return alpha_mv.mv_##NAME(addr); \
}
#define REMAP2(TYPE, NAME, QUAL) \
static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \
{ \
alpha_mv.mv_##NAME(b, addr); \
}
REMAP1(unsigned int, ioread8, /**/)
REMAP1(unsigned int, ioread16, /**/)
REMAP1(unsigned int, ioread32, /**/)
REMAP1(u8, readb, const volatile)
REMAP1(u16, readw, const volatile)
REMAP1(u32, readl, const volatile)
REMAP1(u64, readq, const volatile)
REMAP2(u8, iowrite8, /**/)
REMAP2(u16, iowrite16, /**/)
REMAP2(u32, iowrite32, /**/)
REMAP2(u8, writeb, volatile)
REMAP2(u16, writew, volatile)
REMAP2(u32, writel, volatile)
REMAP2(u64, writeq, volatile)
#undef REMAP1
#undef REMAP2
extern inline void __iomem *generic_ioportmap(unsigned long a)
{
return alpha_mv.mv_ioportmap(a);
}
static inline void __iomem *generic_ioremap(unsigned long a, unsigned long s)
{
return alpha_mv.mv_ioremap(a, s);
}
static inline void generic_iounmap(volatile void __iomem *a)
{
return alpha_mv.mv_iounmap(a);
}
static inline int generic_is_ioaddr(unsigned long a)
{
return alpha_mv.mv_is_ioaddr(a);
}
static inline int generic_is_mmio(const volatile void __iomem *a)
{
return alpha_mv.mv_is_mmio(a);
}
#define __IO_PREFIX generic
#define generic_trivial_rw_bw 0
#define generic_trivial_rw_lq 0
#define generic_trivial_io_bw 0
#define generic_trivial_io_lq 0
#define generic_trivial_iounmap 0
#else
#if defined(CONFIG_ALPHA_APECS)
# include <asm/core_apecs.h>
#elif defined(CONFIG_ALPHA_CIA)
# include <asm/core_cia.h>
#elif defined(CONFIG_ALPHA_IRONGATE)
# include <asm/core_irongate.h>
#elif defined(CONFIG_ALPHA_JENSEN)
# include <asm/jensen.h>
#elif defined(CONFIG_ALPHA_LCA)
# include <asm/core_lca.h>
#elif defined(CONFIG_ALPHA_MARVEL)
# include <asm/core_marvel.h>
#elif defined(CONFIG_ALPHA_MCPCIA)
# include <asm/core_mcpcia.h>
#elif defined(CONFIG_ALPHA_POLARIS)
# include <asm/core_polaris.h>
#elif defined(CONFIG_ALPHA_T2)
# include <asm/core_t2.h>
#elif defined(CONFIG_ALPHA_TSUNAMI)
# include <asm/core_tsunami.h>
#elif defined(CONFIG_ALPHA_TITAN)
# include <asm/core_titan.h>
#elif defined(CONFIG_ALPHA_WILDFIRE)
# include <asm/core_wildfire.h>
#else
#error "What system is this?"
#endif
#endif /* GENERIC */
/*
* We always have external versions of these routines.
*/
extern u8 inb(unsigned long port);
extern u16 inw(unsigned long port);
extern u32 inl(unsigned long port);
extern void outb(u8 b, unsigned long port);
extern void outw(u16 b, unsigned long port);
extern void outl(u32 b, unsigned long port);
extern u8 readb(const volatile void __iomem *addr);
extern u16 readw(const volatile void __iomem *addr);
extern u32 readl(const volatile void __iomem *addr);
extern u64 readq(const volatile void __iomem *addr);
extern void writeb(u8 b, volatile void __iomem *addr);
extern void writew(u16 b, volatile void __iomem *addr);
extern void writel(u32 b, volatile void __iomem *addr);
extern void writeq(u64 b, volatile void __iomem *addr);
extern u8 __raw_readb(const volatile void __iomem *addr);
extern u16 __raw_readw(const volatile void __iomem *addr);
extern u32 __raw_readl(const volatile void __iomem *addr);
extern u64 __raw_readq(const volatile void __iomem *addr);
extern void __raw_writeb(u8 b, volatile void __iomem
|