From 24339348b9153047c08b5879bc69d3327cb07783 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Thu, 14 Mar 2019 08:38:43 -0700 Subject: perf vendor events intel: Update Skylake events to v42 Signed-off-by: Andi Kleen Cc: Kan Liang Cc: Jiri Olsa Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/skylake/cache.json | 2193 +++++++++++++++++++- .../perf/pmu-events/arch/x86/skylake/frontend.json | 14 +- tools/perf/pmu-events/arch/x86/skylake/memory.json | 1121 +++++++++- .../perf/pmu-events/arch/x86/skylake/pipeline.json | 39 +- 4 files changed, 3181 insertions(+), 186 deletions(-) (limited to 'tools/perf/pmu-events') diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json index 54bfe9e4045c..720458139049 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -60,10 +60,10 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "Counts the number of demand Data Read requests that hit L2 cache. Only non rejected loads are counted.", + "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", "EventCode": "0x24", "Counter": "0,1,2,3", - "UMask": "0x41", + "UMask": "0xc1", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "SampleAfterValue": "200003", "BriefDescription": "Demand Data Read requests that hit L2 cache", @@ -73,7 +73,7 @@ "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", "EventCode": "0x24", "Counter": "0,1,2,3", - "UMask": "0x42", + "UMask": "0xc2", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", "BriefDescription": "RFO requests that hit L2 cache", @@ -83,7 +83,7 @@ "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", "EventCode": "0x24", "Counter": "0,1,2,3", - "UMask": "0x44", + "UMask": "0xc4", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", "BriefDescription": "L2 cache hits when fetching instructions, code reads.", @@ -482,7 +482,7 @@ }, { "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.\r\n", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", "EventCode": "0xD1", "Counter": "0,1,2,3", "UMask": "0x1", @@ -554,7 +554,7 @@ }, { "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. \r\n", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", "EventCode": "0xD1", "Counter": "0,1,2,3", "UMask": "0x40", @@ -661,13 +661,13 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache.", + "PublicDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", "EventCode": "0xF2", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "L2_LINES_OUT.USELESS_PREF", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache", + "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { @@ -690,249 +690,2238 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fc0400001 ", + "MSRValue": "0x3FC0408000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & ANY_SNOOP", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000400001 ", + "MSRValue": "0x1000408000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_HITM", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400400001 ", + "MSRValue": "0x0400408000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200400001 ", + "MSRValue": "0x0200408000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_MISS", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400001 ", + "MSRValue": "0x0100408000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080400001 ", + "MSRValue": "0x0080408000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NONE", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fc01c0001 ", + "MSRValue": "0x0040408000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L3_HIT & ANY_SNOOP", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10001c0001 ", + "MSRValue": "0x3FC01C8000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HITM", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04001c0001 ", + "MSRValue": "0x10001C8000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02001c0001 ", + "MSRValue": "0x04001C8000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response.", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01001c0001 ", + "MSRValue": "0x02001C8000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00801c0001 ", + "MSRValue": "0x01001C8000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_NONE", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fc0020001 ", + "MSRValue": "0x00801C8000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020001 ", + "MSRValue": "0x00401C8000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020001 ", + "MSRValue": "0x3FC0108000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020001 ", + "MSRValue": "0x1000108000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020001 ", + "MSRValue": "0x0400108000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "BriefDescription": "Counts any other requests", "Offcore": "1", "CounterHTOff": "0,1,2,3" }, { - "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "PublicDescription": "Counts any other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020001 ", + "MSRValue": "0x0200108000", "Counter": "0,1,2,3", "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6, 0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts any other requests", + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100108000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts any other requests", + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080108000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6, 0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts any other requests", + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040108000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts any other requests", + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3FC0088000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6, 0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts any other requests", + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000088000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6, 0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts any other requests", + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400088000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6, 0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + 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