From 2fbc5bdc8fd1afa6d47223f6a4251f04c7d8fe7c Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Fri, 16 Mar 2018 15:34:07 -0700 Subject: usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fields Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register fields for DWC_usb31 is as follows: +-------+--------------------------+----------------------------------+ | BITS | Name | Description | +=======+==========================+==================================+ | 31:27 | reserved | | | 26 | UsbRxPktCntSel | Async ESS receive packet | | | | threshold enable | | 25:21 | UsbRxPktCnt | Async ESS receive packet | | | | threshold count | | 20:16 | UsbMaxRxBurstSize | Async ESS Max receive burst size | | 15 | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold enable | | 14:13 | UsbRxThrNumPkt_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold count | | 12:11 | reserved | | | 10 | UsbRxThrNumPktSel_Prd | Periodic ESS receive packet | | | | threshold enable | | 9:5 | UsbRxThrNumPkt_Prd | Periodic ESS receive packet | | | | threshold count | | 4:0 | UsbMaxRxBurstSize_Prd | Max periodic ESS RX burst size | +-------+--------------------------+----------------------------------+ Signed-off-by: Thinh Nguyen Signed-off-by: Felipe Balbi --- drivers/usb/dwc3/core.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/usb/dwc3/core.h') diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 1ecdc062df58..8c3f28f3eff8 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -178,6 +178,16 @@ #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) +/* Global RX Threshold Configuration Register for DWC_usb31 only */ +#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) +#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) +#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) +#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) +#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) +#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) +#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) +#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) + /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) #define DWC3_GCTL_U2RSTECN BIT(16) -- cgit v1.2.3