From 8b526ae4ddd7a62397d99856079b59eda5d09360 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Fri, 16 Jul 2010 10:19:41 +0900 Subject: ARM: SAMSUNG: serial: Add FRACVAL support for newer UART Add support for the FRACVAL register on the newer UART blocks which provides the same function as UDIVSLOT register but the FRACVAL is easier to implement. To support UDIVSLOT register, UDIVSLOT table search is necessary though supporting FRACVAL only needs the index value of UDIVSLOT table. Signed-off-by: Jongpill Lee Acked-by: Changhwan Youn Signed-off-by: Kukjin Kim --- drivers/serial/samsung.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/serial') diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index a9d6c5626a0a..b1156ba8ad14 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c @@ -705,8 +705,13 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, if (ourport->info->has_divslot) { unsigned int div = ourport->baudclk_rate / baud; - udivslot = udivslot_table[div & 15]; - dbg("udivslot = %04x (div %d)\n", udivslot, div & 15); + if (cfg->has_fracval) { + udivslot = (div & 15); + dbg("fracval = %04x\n", udivslot); + } else { + udivslot = udivslot_table[div & 15]; + dbg("udivslot = %04x (div %d)\n", udivslot, div & 15); + } } switch (termios->c_cflag & CSIZE) { -- cgit v1.2.3 From acfdc56d541517266eeeeca3a4e5baafaa01c2a1 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Fri, 16 Jul 2010 15:07:37 +0900 Subject: ARM: S5PV310: Add serial port support This patch adds UART serial port support for S5PV310. In the case of that serial device has just one clock source, driver can not control clock source. So add check function in get_clksrc and set_clksrc. Signed-off-by: Jongpill Lee Acked-by: Changhwan Youn Signed-off-by: Kukjin Kim --- drivers/serial/Kconfig | 4 ++-- drivers/serial/s5pv210.c | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers/serial') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b23165bc5dc..aa220108cece 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -544,8 +544,8 @@ config SERIAL_S3C6400 config SERIAL_S5PV210 tristate "Samsung S5PV210 Serial port support" - depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442) - select SERIAL_SAMSUNG_UARTS_4 if CPU_S5PV210 + depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_S5PV310) + select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_S5PV310) default y help Serial port support for Samsung's S5P Family of SoC's diff --git a/drivers/serial/s5pv210.c b/drivers/serial/s5pv210.c index 4a789e5361a4..6ebccd70a707 100644 --- a/drivers/serial/s5pv210.c +++ b/drivers/serial/s5pv210.c @@ -28,8 +28,12 @@ static int s5pv210_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *clk) { + struct s3c2410_uartcfg *cfg = port->dev->platform_data; unsigned long ucon = rd_regl(port, S3C2410_UCON); + if ((cfg->clocks_size) == 1) + return 0; + if (strcmp(clk->name, "pclk") == 0) ucon &= ~S5PV210_UCON_CLKMASK; else if (strcmp(clk->name, "uclk1") == 0) @@ -47,10 +51,14 @@ static int s5pv210_serial_setsource(struct uart_port *port, static int s5pv210_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *clk) { + struct s3c2410_uartcfg *cfg = port->dev->platform_data; u32 ucon = rd_regl(port, S3C2410_UCON); clk->divisor = 1; + if ((cfg->clocks_size) == 1) + return 0; + switch (ucon & S5PV210_UCON_CLKMASK) { case S5PV210_UCON_PCLK: clk->name = "pclk"; -- cgit v1.2.3