From 023e06dfa6882f500b9c86fd61f0b1913aa07f36 Mon Sep 17 00:00:00 2001 From: Hakjoo Kim Date: Sun, 15 Mar 2015 23:00:32 +0100 Subject: pinctrl: exynos: add exynos5410 SoC specific data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Samsung EXYNOS5410 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5410. Signed-off-by: Hakjoo Kim [AF: Rebased onto Exynos5260, irq_chip consolidation, const'ification] Signed-off-by: Andreas Färber Acked-by: Tomasz Figa Tested-by: Pavel Fedin [k.kozlowski: Rebased on current v4.3] Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-exynos.c | 103 ++++++++++++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 106 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 71ccf6a90b22..16e2293cc2bc 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -1150,6 +1150,109 @@ const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { }, }; +/* pin banks of exynos5410 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), + EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), + EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), + EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), + EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), + EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), + EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5410 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), + EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), +}; + +/* pin banks of exynos5410 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5410 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5410_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5410_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5410_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5410_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + /* pin banks of exynos5420 pin-controller 0 */ static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 3f622ccd8eab..48294e7449a4 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1222,6 +1222,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos5250_pin_ctrl }, { .compatible = "samsung,exynos5260-pinctrl", .data = (void *)exynos5260_pin_ctrl }, + { .compatible = "samsung,exynos5410-pinctrl", + .data = (void *)exynos5410_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,exynos5433-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index c1239ff6157d..cd31bfaf62cb 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -270,6 +270,7 @@ extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[]; +extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos7_pin_ctrl[]; -- cgit v1.2.3 From f10a2585811ebd503ddf8ebcc9a32166c7b4b05f Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 5 Nov 2015 17:10:22 +0100 Subject: pinctrl: Delete unnecessary checks The pinctrl_unregister() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | 3 +-- drivers/pinctrl/pinctrl-single.c | 5 +---- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index 12a48f498b75..663ad0a34674 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -638,8 +638,7 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip) { - if (chip->pctl) - pinctrl_unregister(chip->pctl); + pinctrl_unregister(chip->pctl); } struct cygnus_gpio_data { diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index ef04b962c3d5..d24e5f1d1525 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1484,10 +1484,7 @@ static void pcs_irq_free(struct pcs_device *pcs) static void pcs_free_resources(struct pcs_device *pcs) { pcs_irq_free(pcs); - - if (pcs->pctl) - pinctrl_unregister(pcs->pctl); - + pinctrl_unregister(pcs->pctl); pcs_free_funcs(pcs); pcs_free_pingroups(pcs); } -- cgit v1.2.3 From b04a23b05609b35365127ad8906c55866eb47fe7 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Tue, 17 Nov 2015 14:33:41 -0800 Subject: pinctrl: mediatek: fix a memleak when do dt maps. configs will kmemdup to dup_configs in pictrl util function. So configs need to be freed. Signed-off-by: Hongzhou Yang Reviewed-by: Daniel Kurtz Reviewed-by: Matthias Brugger Reviewed-by: Yingjoe Chen Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index f307f1d27d64..3bb4a2ae8ee4 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -509,6 +509,9 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, err = pinconf_generic_parse_dt_config(node, pctldev, &configs, &num_configs); + if (err) + return err; + if (num_configs) has_config = 1; @@ -520,21 +523,23 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (has_config && num_pins >= 1) maps_per_pin++; - if (!num_pins || !maps_per_pin) - return -EINVAL; + if (!num_pins || !maps_per_pin) { + err = -EINVAL; + goto exit; + } reserve = num_pins * maps_per_pin; err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, reserve); if (err < 0) - goto fail; + goto exit; for (i = 0; i < num_pins; i++) { err = of_property_read_u32_index(node, "pinmux", i, &pinfunc); if (err) - goto fail; + goto exit; pin = MTK_GET_PIN_NO(pinfunc); func = MTK_GET_PIN_FUNC(pinfunc); @@ -543,20 +548,21 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, func >= ARRAY_SIZE(mtk_gpio_functions)) { dev_err(pctl->dev, "invalid pins value.\n"); err = -EINVAL; - goto fail; + goto exit; } grp = mtk_pctrl_find_group_by_pin(pctl, pin); if (!grp) { dev_err(pctl->dev, "unable to match pin %d to group\n", pin); - return -EINVAL; + err = -EINVAL; + goto exit; } err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, reserved_maps, num_maps); if (err < 0) - goto fail; + goto exit; if (has_config) { err = pinctrl_utils_add_map_configs(pctldev, map, @@ -564,13 +570,14 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, configs, num_configs, PIN_MAP_TYPE_CONFIGS_GROUP); if (err < 0) - goto fail; + goto exit; } } - return 0; + err = 0; -fail: +exit: + kfree(configs); return err; } -- cgit v1.2.3 From e1aaaf3ff311ce03401965a38b33aceac4e51951 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:15 +0530 Subject: pinctrl: use ngpios propety from DT Since identical hardware is used in several instances and every instance will have different in-use pins. Hence extracting this number from DT via "ngpios" property. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | 45 +++++++------------------------ 1 file changed, 9 insertions(+), 36 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index 663ad0a34674..f19283aa8419 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -641,35 +641,11 @@ static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip) pinctrl_unregister(chip->pctl); } -struct cygnus_gpio_data { - unsigned num_gpios; -}; - -static const struct cygnus_gpio_data cygnus_cmm_gpio_data = { - .num_gpios = 24, -}; - -static const struct cygnus_gpio_data cygnus_asiu_gpio_data = { - .num_gpios = 146, -}; - -static const struct cygnus_gpio_data cygnus_crmu_gpio_data = { - .num_gpios = 6, -}; - static const struct of_device_id cygnus_gpio_of_match[] = { - { - .compatible = "brcm,cygnus-ccm-gpio", - .data = &cygnus_cmm_gpio_data, - }, - { - .compatible = "brcm,cygnus-asiu-gpio", - .data = &cygnus_asiu_gpio_data, - }, - { - .compatible = "brcm,cygnus-crmu-gpio", - .data = &cygnus_crmu_gpio_data, - } + { .compatible = "brcm,cygnus-ccm-gpio" }, + { .compatible = "brcm,cygnus-asiu-gpio" }, + { .compatible = "brcm,cygnus-crmu-gpio" }, + { } }; static int cygnus_gpio_probe(struct platform_device *pdev) @@ -680,14 +656,6 @@ static int cygnus_gpio_probe(struct platform_device *pdev) struct gpio_chip *gc; u32 ngpios; int irq, ret; - const struct of_device_id *match; - const struct cygnus_gpio_data *gpio_data; - - match = of_match_device(cygnus_gpio_of_match, dev); - if (!match) - return -ENODEV; - gpio_data = match->data; - ngpios = gpio_data->num_gpios; chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (!chip) @@ -712,6 +680,11 @@ static int cygnus_gpio_probe(struct platform_device *pdev) } } + if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { + dev_err(&pdev->dev, "missing ngpios DT property\n"); + return -ENODEV; + } + spin_lock_init(&chip->lock); gc = &chip->gc; -- cgit v1.2.3 From 462de629942212d90e6c915eca3eaebb45b647a3 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:16 +0530 Subject: pinctrl: Add new compatible string to GPIO controller driver This compatible string should be used for all new iproc based future SoCs having the same GPIO controller hardware. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index f19283aa8419..f60ec8edead1 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -645,6 +645,7 @@ static const struct of_device_id cygnus_gpio_of_match[] = { { .compatible = "brcm,cygnus-ccm-gpio" }, { .compatible = "brcm,cygnus-asiu-gpio" }, { .compatible = "brcm,cygnus-crmu-gpio" }, + { .compatible = "brcm,iproc-gpio" }, { } }; -- cgit v1.2.3 From afc8c78d179d36b85b648dca865e56040afc5f2d Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:17 +0530 Subject: gpio: Rename func/macro/var to IP-block,iproc Change functions, macros and variables name from cygnus to IP block, iproc, so that it could be used in all iproc based future SoCs having same GPIO controller block. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | 306 +++++++++++++++--------------- 1 file changed, 154 insertions(+), 152 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index f60ec8edead1..fa66c3e05cc3 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -10,14 +10,16 @@ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * This file contains the Broadcom Cygnus GPIO driver that supports 3 - * GPIO controllers on Cygnus including the ASIU GPIO controller, the + * This file contains the Broadcom Iproc GPIO driver that supports 3 + * GPIO controllers on Iproc including the ASIU GPIO controller, the * chipCommonG GPIO controller, and the always-on GPIO controller. Basic * PINCONF such as bias pull up/down, and drive strength are also supported * in this driver. * - * Pins from the ASIU GPIO can be individually muxed to GPIO function, - * through the interaction with the Cygnus IOMUX controller + * It provides the functionality where pins from the GPIO can be + * individually muxed to GPIO function, if individual pad + * configuration is supported, through the interaction with respective + * SoCs IOMUX controller. */ #include @@ -34,42 +36,42 @@ #include "../pinctrl-utils.h" -#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00 -#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04 -#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08 -#define CYGNUS_GPIO_INT_TYPE_OFFSET 0x0c -#define CYGNUS_GPIO_INT_DE_OFFSET 0x10 -#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14 -#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18 -#define CYGNUS_GPIO_INT_STAT_OFFSET 0x1c -#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20 -#define CYGNUS_GPIO_INT_CLR_OFFSET 0x24 -#define CYGNUS_GPIO_PAD_RES_OFFSET 0x34 -#define CYGNUS_GPIO_RES_EN_OFFSET 0x38 +#define IPROC_GPIO_DATA_IN_OFFSET 0x00 +#define IPROC_GPIO_DATA_OUT_OFFSET 0x04 +#define IPROC_GPIO_OUT_EN_OFFSET 0x08 +#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c +#define IPROC_GPIO_INT_DE_OFFSET 0x10 +#define IPROC_GPIO_INT_EDGE_OFFSET 0x14 +#define IPROC_GPIO_INT_MSK_OFFSET 0x18 +#define IPROC_GPIO_INT_STAT_OFFSET 0x1c +#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20 +#define IPROC_GPIO_INT_CLR_OFFSET 0x24 +#define IPROC_GPIO_PAD_RES_OFFSET 0x34 +#define IPROC_GPIO_RES_EN_OFFSET 0x38 /* drive strength control for ASIU GPIO */ -#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 +#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 /* drive strength control for CCM/CRMU (AON) GPIO */ -#define CYGNUS_GPIO_DRV0_CTRL_OFFSET 0x00 +#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00 #define GPIO_BANK_SIZE 0x200 #define NGPIOS_PER_BANK 32 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) -#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) -#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) +#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) +#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) #define GPIO_DRV_STRENGTH_BIT_SHIFT 20 #define GPIO_DRV_STRENGTH_BITS 3 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) /* - * Cygnus GPIO core + * Iproc GPIO core * * @dev: pointer to device - * @base: I/O register base for Cygnus GPIO controller - * @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that + * @base: I/O register base for Iproc GPIO controller + * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that * has the PINCONF support implemented outside of the GPIO block * @lock: lock to protect access to I/O registers * @gc: GPIO chip @@ -79,7 +81,7 @@ * @pctl: pointer to pinctrl_dev * @pctldesc: pinctrl descriptor */ -struct cygnus_gpio { +struct iproc_gpio { struct device *dev; void __iomem *base; @@ -96,33 +98,33 @@ struct cygnus_gpio { struct pinctrl_desc pctldesc; }; -static inline struct cygnus_gpio *to_cygnus_gpio(struct gpio_chip *gc) +static inline struct iproc_gpio *to_iproc_gpio(struct gpio_chip *gc) { - return container_of(gc, struct cygnus_gpio, gc); + return container_of(gc, struct iproc_gpio, gc); } /* * Mapping from PINCONF pins to GPIO pins is 1-to-1 */ -static inline unsigned cygnus_pin_to_gpio(unsigned pin) +static inline unsigned iproc_pin_to_gpio(unsigned pin) { return pin; } /** - * cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a - * Cygnus GPIO register + * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a + * Iproc GPIO register * - * @cygnus_gpio: Cygnus GPIO device + * @iproc_gpio: Iproc GPIO device * @reg: register offset * @gpio: GPIO pin * @set: set or clear */ -static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg, +static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, unsigned gpio, bool set) { - unsigned int offset = CYGNUS_GPIO_REG(gpio, reg); - unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + unsigned int offset = IPROC_GPIO_REG(gpio, reg); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); u32 val; val = readl(chip->base + offset); @@ -133,19 +135,19 @@ static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg, writel(val, chip->base + offset); } -static inline bool cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg, +static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, unsigned gpio) { - unsigned int offset = CYGNUS_GPIO_REG(gpio, reg); - unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + unsigned int offset = IPROC_GPIO_REG(gpio, reg); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); return !!(readl(chip->base + offset) & BIT(shift)); } -static void cygnus_gpio_irq_handler(struct irq_desc *desc) +static void iproc_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); struct irq_chip *irq_chip = irq_desc_get_chip(desc); int i, bit; @@ -154,7 +156,7 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc) /* go through the entire GPIO banks and handle all interrupts */ for (i = 0; i < chip->num_banks; i++) { unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + - CYGNUS_GPIO_INT_MSTAT_OFFSET); + IPROC_GPIO_INT_MSTAT_OFFSET); for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { unsigned pin = NGPIOS_PER_BANK * i + bit; @@ -165,7 +167,7 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc) * handler, so we do not leave any window */ writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + - CYGNUS_GPIO_INT_CLR_OFFSET); + IPROC_GPIO_INT_CLR_OFFSET); generic_handle_irq(child_irq); } @@ -175,60 +177,60 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc) } -static void cygnus_gpio_irq_ack(struct irq_data *d) +static void iproc_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = d->hwirq; - unsigned int offset = CYGNUS_GPIO_REG(gpio, - CYGNUS_GPIO_INT_CLR_OFFSET); - unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + unsigned int offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_INT_CLR_OFFSET); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); u32 val = BIT(shift); writel(val, chip->base + offset); } /** - * cygnus_gpio_irq_set_mask - mask/unmask a GPIO interrupt + * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt * * @d: IRQ chip data * @unmask: mask/unmask GPIO interrupt */ -static void cygnus_gpio_irq_set_mask(struct irq_data *d, bool unmask) +static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = d->hwirq; - cygnus_set_bit(chip, CYGNUS_GPIO_INT_MSK_OFFSET, gpio, unmask); + iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); } -static void cygnus_gpio_irq_mask(struct irq_data *d) +static void iproc_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_gpio_irq_set_mask(d, false); + iproc_gpio_irq_set_mask(d, false); spin_unlock_irqrestore(&chip->lock, flags); } -static void cygnus_gpio_irq_unmask(struct irq_data *d) +static void iproc_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_gpio_irq_set_mask(d, true); + iproc_gpio_irq_set_mask(d, true); spin_unlock_irqrestore(&chip->lock, flags); } -static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) +static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = d->hwirq; bool level_triggered = false; bool dual_edge = false; @@ -263,10 +265,10 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) } spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_INT_TYPE_OFFSET, gpio, + iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio, level_triggered); - cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge); - cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio, + iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); + iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, rising_or_high); spin_unlock_irqrestore(&chip->lock, flags); @@ -277,32 +279,32 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) return 0; } -static struct irq_chip cygnus_gpio_irq_chip = { - .name = "bcm-cygnus-gpio", - .irq_ack = cygnus_gpio_irq_ack, - .irq_mask = cygnus_gpio_irq_mask, - .irq_unmask = cygnus_gpio_irq_unmask, - .irq_set_type = cygnus_gpio_irq_set_type, +static struct irq_chip iproc_gpio_irq_chip = { + .name = "bcm-iproc-gpio", + .irq_ack = iproc_gpio_irq_ack, + .irq_mask = iproc_gpio_irq_mask, + .irq_unmask = iproc_gpio_irq_unmask, + .irq_set_type = iproc_gpio_irq_set_type, }; /* - * Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO + * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO */ -static int cygnus_gpio_request(struct gpio_chip *gc, unsigned offset) +static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = gc->base + offset; - /* not all Cygnus GPIO pins can be muxed individually */ + /* not all Iproc GPIO pins can be muxed individually */ if (!chip->pinmux_is_supported) return 0; return pinctrl_request_gpio(gpio); } -static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset) +static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = gc->base + offset; if (!chip->pinmux_is_supported) @@ -311,13 +313,13 @@ static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset) pinctrl_free_gpio(gpio); } -static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) +static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, false); + iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false); spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, "gpio:%u set input\n", gpio); @@ -325,15 +327,15 @@ static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) return 0; } -static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, +static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, int val) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, true); - cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); + iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true); + iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); @@ -341,29 +343,29 @@ static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, return 0; } -static void cygnus_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) +static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); + iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); } -static int cygnus_gpio_get(struct gpio_chip *gc, unsigned gpio) +static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); - unsigned int offset = CYGNUS_GPIO_REG(gpio, - CYGNUS_GPIO_DATA_IN_OFFSET); - unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned int offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_DATA_IN_OFFSET); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); return !!(readl(chip->base + offset) & BIT(shift)); } -static int cygnus_get_groups_count(struct pinctrl_dev *pctldev) +static int iproc_get_groups_count(struct pinctrl_dev *pctldev) { return 1; } @@ -372,20 +374,20 @@ static int cygnus_get_groups_count(struct pinctrl_dev *pctldev) * Only one group: "gpio_grp", since this local pinctrl device only performs * GPIO specific PINCONF configurations */ -static const char *cygnus_get_group_name(struct pinctrl_dev *pctldev, +static const char *iproc_get_group_name(struct pinctrl_dev *pctldev, unsigned selector) { return "gpio_grp"; } -static const struct pinctrl_ops cygnus_pctrl_ops = { - .get_groups_count = cygnus_get_groups_count, - .get_group_name = cygnus_get_group_name, +static const struct pinctrl_ops iproc_pctrl_ops = { + .get_groups_count = iproc_get_groups_count, + .get_group_name = iproc_get_group_name, .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .dt_free_map = pinctrl_utils_dt_free_map, }; -static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio, +static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, bool disable, bool pull_up) { unsigned long flags; @@ -393,11 +395,11 @@ static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio, spin_lock_irqsave(&chip->lock, flags); if (disable) { - cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, false); + iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false); } else { - cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio, + iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, pull_up); - cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, true); + iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true); } spin_unlock_irqrestore(&chip->lock, flags); @@ -407,18 +409,18 @@ static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio, return 0; } -static void cygnus_gpio_get_pull(struct cygnus_gpio *chip, unsigned gpio, +static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, bool *disable, bool *pull_up) { unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - *disable = !cygnus_get_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio); - *pull_up = cygnus_get_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio); + *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); + *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); spin_unlock_irqrestore(&chip->lock, flags); } -static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio, +static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, unsigned strength) { void __iomem *base; @@ -432,14 +434,14 @@ static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio, if (chip->io_ctrl) { base = chip->io_ctrl; - offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET; + offset = IPROC_GPIO_DRV0_CTRL_OFFSET; } else { base = chip->base; - offset = CYGNUS_GPIO_REG(gpio, - CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET); + offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); } - shift = CYGNUS_GPIO_SHIFT(gpio); + shift = IPROC_GPIO_SHIFT(gpio); dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, strength); @@ -458,7 +460,7 @@ static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio, return 0; } -static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio, +static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, u16 *strength) { void __iomem *base; @@ -468,14 +470,14 @@ static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio, if (chip->io_ctrl) { base = chip->io_ctrl; - offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET; + offset = IPROC_GPIO_DRV0_CTRL_OFFSET; } else { base = chip->base; - offset = CYGNUS_GPIO_REG(gpio, - CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET); + offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); } - shift = CYGNUS_GPIO_SHIFT(gpio); + shift = IPROC_GPIO_SHIFT(gpio); spin_lock_irqsave(&chip->lock, flags); *strength = 0; @@ -493,40 +495,40 @@ static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio, return 0; } -static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, +static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { - struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); - unsigned gpio = cygnus_pin_to_gpio(pin); + unsigned gpio = iproc_pin_to_gpio(pin); u16 arg; bool disable, pull_up; int ret; switch (param) { case PIN_CONFIG_BIAS_DISABLE: - cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); if (disable) return 0; else return -EINVAL; case PIN_CONFIG_BIAS_PULL_UP: - cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); if (!disable && pull_up) return 0; else return -EINVAL; case PIN_CONFIG_BIAS_PULL_DOWN: - cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); if (!disable && !pull_up) return 0; else return -EINVAL; case PIN_CONFIG_DRIVE_STRENGTH: - ret = cygnus_gpio_get_strength(chip, gpio, &arg); + ret = iproc_gpio_get_strength(chip, gpio, &arg); if (ret) return ret; else @@ -541,13 +543,13 @@ static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, return -ENOTSUPP; } -static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, +static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs) { - struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param; u16 arg; - unsigned i, gpio = cygnus_pin_to_gpio(pin); + unsigned i, gpio = iproc_pin_to_gpio(pin); int ret = -ENOTSUPP; for (i = 0; i < num_configs; i++) { @@ -556,25 +558,25 @@ static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - ret = cygnus_gpio_set_pull(chip, gpio, true, false); + ret = iproc_gpio_set_pull(chip, gpio, true, false); if (ret < 0) goto out; break; case PIN_CONFIG_BIAS_PULL_UP: - ret = cygnus_gpio_set_pull(chip, gpio, false, true); + ret = iproc_gpio_set_pull(chip, gpio, false, true); if (ret < 0) goto out; break; case PIN_CONFIG_BIAS_PULL_DOWN: - ret = cygnus_gpio_set_pull(chip, gpio, false, false); + ret = iproc_gpio_set_pull(chip, gpio, false, false); if (ret < 0) goto out; break; case PIN_CONFIG_DRIVE_STRENGTH: - ret = cygnus_gpio_set_strength(chip, gpio, arg); + ret = iproc_gpio_set_strength(chip, gpio, arg); if (ret < 0) goto out; break; @@ -589,20 +591,20 @@ out: return ret; } -static const struct pinconf_ops cygnus_pconf_ops = { +static const struct pinconf_ops iproc_pconf_ops = { .is_generic = true, - .pin_config_get = cygnus_pin_config_get, - .pin_config_set = cygnus_pin_config_set, + .pin_config_get = iproc_pin_config_get, + .pin_config_set = iproc_pin_config_set, }; /* - * Cygnus GPIO controller supports some PINCONF related configurations such as + * Iproc GPIO controller supports some PINCONF related configurations such as * pull up, pull down, and drive strength, when the pin is configured to GPIO * * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the * local GPIO pins */ -static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) +static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) { struct pinctrl_desc *pctldesc = &chip->pctldesc; struct pinctrl_pin_desc *pins; @@ -622,10 +624,10 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) } pctldesc->name = dev_name(chip->dev); - pctldesc->pctlops = &cygnus_pctrl_ops; + pctldesc->pctlops = &iproc_pctrl_ops; pctldesc->pins = pins; pctldesc->npins = gc->ngpio; - pctldesc->confops = &cygnus_pconf_ops; + pctldesc->confops = &iproc_pconf_ops; chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); if (IS_ERR(chip->pctl)) { @@ -636,12 +638,12 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) return 0; } -static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip) +static void iproc_gpio_unregister_pinconf(struct cygnus_gpio *chip) { pinctrl_unregister(chip->pctl); } -static const struct of_device_id cygnus_gpio_of_match[] = { +static const struct of_device_id iproc_gpio_of_match[] = { { .compatible = "brcm,cygnus-ccm-gpio" }, { .compatible = "brcm,cygnus-asiu-gpio" }, { .compatible = "brcm,cygnus-crmu-gpio" }, @@ -649,11 +651,11 @@ static const struct of_device_id cygnus_gpio_of_match[] = { { } }; -static int cygnus_gpio_probe(struct platform_device *pdev) +static int iproc_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *res; - struct cygnus_gpio *chip; + struct iproc_gpio *chip; struct gpio_chip *gc; u32 ngpios; int irq, ret; @@ -695,12 +697,12 @@ static int cygnus_gpio_probe(struct platform_device *pdev) gc->label = dev_name(dev); gc->dev = dev; gc->of_node = dev->of_node; - gc->request = cygnus_gpio_request; - gc->free = cygnus_gpio_free; - gc->direction_input = cygnus_gpio_direction_input; - gc->direction_output = cygnus_gpio_direction_output; - gc->set = cygnus_gpio_set; - gc->get = cygnus_gpio_get; + gc->request = iproc_gpio_request; + gc->free = iproc_gpio_free; + gc->direction_input = iproc_gpio_direction_input; + gc->direction_output = iproc_gpio_direction_output; + gc->set = iproc_gpio_set; + gc->get = iproc_gpio_get; chip->pinmux_is_supported = of_property_read_bool(dev->of_node, "gpio-ranges"); @@ -711,7 +713,7 @@ static int cygnus_gpio_probe(struct platform_device *pdev) return ret; } - ret = cygnus_gpio_register_pinconf(chip); + ret = iproc_gpio_register_pinconf(chip); if (ret) { dev_err(dev, "unable to register pinconf\n"); goto err_rm_gpiochip; @@ -720,21 +722,21 @@ static int cygnus_gpio_probe(struct platform_device *pdev) /* optional GPIO interrupt support */ irq = platform_get_irq(pdev, 0); if (irq) { - ret = gpiochip_irqchip_add(gc, &cygnus_gpio_irq_chip, 0, + ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0, handle_simple_irq, IRQ_TYPE_NONE); if (ret) { dev_err(dev, "no GPIO irqchip\n"); goto err_unregister_pinconf; } - gpiochip_set_chained_irqchip(gc, &cygnus_gpio_irq_chip, irq, - cygnus_gpio_irq_handler); + gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq, + iproc_gpio_irq_handler); } return 0; err_unregister_pinconf: - cygnus_gpio_unregister_pinconf(chip); + iproc_gpio_unregister_pinconf(chip); err_rm_gpiochip: gpiochip_remove(gc); @@ -742,16 +744,16 @@ err_rm_gpiochip: return ret; } -static struct platform_driver cygnus_gpio_driver = { +static struct platform_driver iproc_gpio_driver = { .driver = { - .name = "cygnus-gpio", - .of_match_table = cygnus_gpio_of_match, + .name = "iproc-gpio", + .of_match_table = iproc_gpio_of_match, }, - .probe = cygnus_gpio_probe, + .probe = iproc_gpio_probe, }; -static int __init cygnus_gpio_init(void) +static int __init iproc_gpio_init(void) { - return platform_driver_probe(&cygnus_gpio_driver, cygnus_gpio_probe); + return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe); } -arch_initcall_sync(cygnus_gpio_init); +arch_initcall_sync(iproc_gpio_init); -- cgit v1.2.3 From 616043d58a89c0966e479a83f64ba8c0ab3e657e Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:19 +0530 Subject: pinctrl: Rename gpio driver from cygnus to iproc Rename gpio driver file name from pinctrl-cygnus-gpio.c to pinctrl-iproc-gpio.c to make it more generic so that all iproc based future SoCs using the same gpio block could use this driver. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Acked-by: Rob Herring Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/Kconfig | 30 +- drivers/pinctrl/bcm/Makefile | 2 +- drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | 759 ------------------------------ drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 758 +++++++++++++++++++++++++++++ 4 files changed, 781 insertions(+), 768 deletions(-) delete mode 100644 drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c create mode 100644 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index cd11d4d9ad58..59495473ed53 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -20,27 +20,41 @@ config PINCTRL_BCM2835 select PINMUX select PINCONF -config PINCTRL_CYGNUS_GPIO - bool "Broadcom Cygnus GPIO (with PINCONF) driver" - depends on OF_GPIO && ARCH_BCM_CYGNUS +config PINCTRL_IPROC_GPIO + bool "Broadcom iProc GPIO (with PINCONF) driver" + depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF - default ARCH_BCM_CYGNUS + default ARCH_BCM_IPROC help - Say yes here to enable the Broadcom Cygnus GPIO driver. + Say yes here to enable the Broadcom iProc GPIO driver. + + The Broadcom iProc based SoCs- Cygnus, NS2, NSP and Stingray, use + same GPIO Controller IP hence this driver could be used for all. The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are supported by this driver. - All 3 Cygnus GPIO controllers support basic PINCONF functions such + The Broadcom NSP has two GPIO controllers including the ChipcommonA + GPIO, the ChipcommonB GPIO. Later controller is supported by this + driver. + + The Broadcom NS2 has two GPIO controller including the CRMU GPIO, + the ChipcommonG GPIO. Both controllers are supported by this driver. + + The Broadcom Stingray GPIO controllers are supported by this driver. + + All above SoCs GPIO controllers support basic PINCONF functions such as bias pull up, pull down, and drive strength configurations, when these pins are muxed to GPIO. - Pins from the ASIU GPIO can be individually muxed to GPIO function, - through interaction with the Cygnus IOMUX controller. + It provides the framework where pins from the individual GPIO can be + individually muxed to GPIO function, through interaction with the + SoCs IOMUX controller. This features could be used only on SoCs which + support individual pin muxing. config PINCTRL_CYGNUS_MUX bool "Broadcom Cygnus IOMUX driver" diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 2b2f70ee804c..9ac6370f1c92 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -2,5 +2,5 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o -obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o +obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c deleted file mode 100644 index fa66c3e05cc3..000000000000 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ /dev/null @@ -1,759 +0,0 @@ -/* - * Copyright (C) 2014-2015 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * This file contains the Broadcom Iproc GPIO driver that supports 3 - * GPIO controllers on Iproc including the ASIU GPIO controller, the - * chipCommonG GPIO controller, and the always-on GPIO controller. Basic - * PINCONF such as bias pull up/down, and drive strength are also supported - * in this driver. - * - * It provides the functionality where pins from the GPIO can be - * individually muxed to GPIO function, if individual pad - * configuration is supported, through the interaction with respective - * SoCs IOMUX controller. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../pinctrl-utils.h" - -#define IPROC_GPIO_DATA_IN_OFFSET 0x00 -#define IPROC_GPIO_DATA_OUT_OFFSET 0x04 -#define IPROC_GPIO_OUT_EN_OFFSET 0x08 -#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c -#define IPROC_GPIO_INT_DE_OFFSET 0x10 -#define IPROC_GPIO_INT_EDGE_OFFSET 0x14 -#define IPROC_GPIO_INT_MSK_OFFSET 0x18 -#define IPROC_GPIO_INT_STAT_OFFSET 0x1c -#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20 -#define IPROC_GPIO_INT_CLR_OFFSET 0x24 -#define IPROC_GPIO_PAD_RES_OFFSET 0x34 -#define IPROC_GPIO_RES_EN_OFFSET 0x38 - -/* drive strength control for ASIU GPIO */ -#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 - -/* drive strength control for CCM/CRMU (AON) GPIO */ -#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00 - -#define GPIO_BANK_SIZE 0x200 -#define NGPIOS_PER_BANK 32 -#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) - -#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) -#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) - -#define GPIO_DRV_STRENGTH_BIT_SHIFT 20 -#define GPIO_DRV_STRENGTH_BITS 3 -#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) - -/* - * Iproc GPIO core - * - * @dev: pointer to device - * @base: I/O register base for Iproc GPIO controller - * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that - * has the PINCONF support implemented outside of the GPIO block - * @lock: lock to protect access to I/O registers - * @gc: GPIO chip - * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs - * @pinmux_is_supported: flag to indicate this GPIO controller contains pins - * that can be individually muxed to GPIO - * @pctl: pointer to pinctrl_dev - * @pctldesc: pinctrl descriptor - */ -struct iproc_gpio { - struct device *dev; - - void __iomem *base; - void __iomem *io_ctrl; - - spinlock_t lock; - - struct gpio_chip gc; - unsigned num_banks; - - bool pinmux_is_supported; - - struct pinctrl_dev *pctl; - struct pinctrl_desc pctldesc; -}; - -static inline struct iproc_gpio *to_iproc_gpio(struct gpio_chip *gc) -{ - return container_of(gc, struct iproc_gpio, gc); -} - -/* - * Mapping from PINCONF pins to GPIO pins is 1-to-1 - */ -static inline unsigned iproc_pin_to_gpio(unsigned pin) -{ - return pin; -} - -/** - * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a - * Iproc GPIO register - * - * @iproc_gpio: Iproc GPIO device - * @reg: register offset - * @gpio: GPIO pin - * @set: set or clear - */ -static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, - unsigned gpio, bool set) -{ - unsigned int offset = IPROC_GPIO_REG(gpio, reg); - unsigned int shift = IPROC_GPIO_SHIFT(gpio); - u32 val; - - val = readl(chip->base + offset); - if (set) - val |= BIT(shift); - else - val &= ~BIT(shift); - writel(val, chip->base + offset); -} - -static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, - unsigned gpio) -{ - unsigned int offset = IPROC_GPIO_REG(gpio, reg); - unsigned int shift = IPROC_GPIO_SHIFT(gpio); - - return !!(readl(chip->base + offset) & BIT(shift)); -} - -static void iproc_gpio_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct iproc_gpio *chip = to_iproc_gpio(gc); - struct irq_chip *irq_chip = irq_desc_get_chip(desc); - int i, bit; - - chained_irq_enter(irq_chip, desc); - - /* go through the entire GPIO banks and handle all interrupts */ - for (i = 0; i < chip->num_banks; i++) { - unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + - IPROC_GPIO_INT_MSTAT_OFFSET); - - for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { - unsigned pin = NGPIOS_PER_BANK * i + bit; - int child_irq = irq_find_mapping(gc->irqdomain, pin); - - /* - * Clear the interrupt before invoking the - * handler, so we do not leave any window - */ - writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + - IPROC_GPIO_INT_CLR_OFFSET); - - generic_handle_irq(child_irq); - } - } - - chained_irq_exit(irq_chip, desc); -} - - -static void iproc_gpio_irq_ack(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = d->hwirq; - unsigned int offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_INT_CLR_OFFSET); - unsigned int shift = IPROC_GPIO_SHIFT(gpio); - u32 val = BIT(shift); - - writel(val, chip->base + offset); -} - -/** - * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt - * - * @d: IRQ chip data - * @unmask: mask/unmask GPIO interrupt - */ -static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = d->hwirq; - - iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); -} - -static void iproc_gpio_irq_mask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_gpio_irq_set_mask(d, false); - spin_unlock_irqrestore(&chip->lock, flags); -} - -static void iproc_gpio_irq_unmask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_gpio_irq_set_mask(d, true); - spin_unlock_irqrestore(&chip->lock, flags); -} - -static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = d->hwirq; - bool level_triggered = false; - bool dual_edge = false; - bool rising_or_high = false; - unsigned long flags; - - switch (type & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_EDGE_RISING: - rising_or_high = true; - break; - - case IRQ_TYPE_EDGE_FALLING: - break; - - case IRQ_TYPE_EDGE_BOTH: - dual_edge = true; - break; - - case IRQ_TYPE_LEVEL_HIGH: - level_triggered = true; - rising_or_high = true; - break; - - case IRQ_TYPE_LEVEL_LOW: - level_triggered = true; - break; - - default: - dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", - type); - return -EINVAL; - } - - spin_lock_irqsave(&chip->lock, flags); - iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio, - level_triggered); - iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); - iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, - rising_or_high); - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, - "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n", - gpio, level_triggered, dual_edge, rising_or_high); - - return 0; -} - -static struct irq_chip iproc_gpio_irq_chip = { - .name = "bcm-iproc-gpio", - .irq_ack = iproc_gpio_irq_ack, - .irq_mask = iproc_gpio_irq_mask, - .irq_unmask = iproc_gpio_irq_unmask, - .irq_set_type = iproc_gpio_irq_set_type, -}; - -/* - * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO - */ -static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = gc->base + offset; - - /* not all Iproc GPIO pins can be muxed individually */ - if (!chip->pinmux_is_supported) - return 0; - - return pinctrl_request_gpio(gpio); -} - -static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = gc->base + offset; - - if (!chip->pinmux_is_supported) - return; - - pinctrl_free_gpio(gpio); -} - -static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false); - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, "gpio:%u set input\n", gpio); - - return 0; -} - -static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, - int val) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true); - iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); - - return 0; -} - -static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); -} - -static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned int offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_DATA_IN_OFFSET); - unsigned int shift = IPROC_GPIO_SHIFT(gpio); - - return !!(readl(chip->base + offset) & BIT(shift)); -} - -static int iproc_get_groups_count(struct pinctrl_dev *pctldev) -{ - return 1; -} - -/* - * Only one group: "gpio_grp", since this local pinctrl device only performs - * GPIO specific PINCONF configurations - */ -static const char *iproc_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return "gpio_grp"; -} - -static const struct pinctrl_ops iproc_pctrl_ops = { - .get_groups_count = iproc_get_groups_count, - .get_group_name = iproc_get_group_name, - .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, - .dt_free_map = pinctrl_utils_dt_free_map, -}; - -static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, - bool disable, bool pull_up) -{ - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - - if (disable) { - iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false); - } else { - iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, - pull_up); - iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true); - } - - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); - - return 0; -} - -static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, - bool *disable, bool *pull_up) -{ - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); - *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); - spin_unlock_irqrestore(&chip->lock, flags); -} - -static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, - unsigned strength) -{ - void __iomem *base; - unsigned int i, offset, shift; - u32 val; - unsigned long flags; - - /* make sure drive strength is supported */ - if (strength < 2 || strength > 16 || (strength % 2)) - return -ENOTSUPP; - - if (chip->io_ctrl) { - base = chip->io_ctrl; - offset = IPROC_GPIO_DRV0_CTRL_OFFSET; - } else { - base = chip->base; - offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); - } - - shift = IPROC_GPIO_SHIFT(gpio); - - dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, - strength); - - spin_lock_irqsave(&chip->lock, flags); - strength = (strength / 2) - 1; - for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { - val = readl(base + offset); - val &= ~BIT(shift); - val |= ((strength >> i) & 0x1) << shift; - writel(val, base + offset); - offset += 4; - } - spin_unlock_irqrestore(&chip->lock, flags); - - return 0; -} - -static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, - u16 *strength) -{ - void __iomem *base; - unsigned int i, offset, shift; - u32 val; - unsigned long flags; - - if (chip->io_ctrl) { - base = chip->io_ctrl; - offset = IPROC_GPIO_DRV0_CTRL_OFFSET; - } else { - base = chip->base; - offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); - } - - shift = IPROC_GPIO_SHIFT(gpio); - - spin_lock_irqsave(&chip->lock, flags); - *strength = 0; - for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { - val = readl(base + offset) & BIT(shift); - val >>= shift; - *strength += (val << i); - offset += 4; - } - - /* convert to mA */ - *strength = (*strength + 1) * 2; - spin_unlock_irqrestore(&chip->lock, flags); - - return 0; -} - -static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *config) -{ - struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - unsigned gpio = iproc_pin_to_gpio(pin); - u16 arg; - bool disable, pull_up; - int ret; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); - if (disable) - return 0; - else - return -EINVAL; - - case PIN_CONFIG_BIAS_PULL_UP: - iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); - if (!disable && pull_up) - return 0; - else - return -EINVAL; - - case PIN_CONFIG_BIAS_PULL_DOWN: - iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); - if (!disable && !pull_up) - return 0; - else - return -EINVAL; - - case PIN_CONFIG_DRIVE_STRENGTH: - ret = iproc_gpio_get_strength(chip, gpio, &arg); - if (ret) - return ret; - else - *config = pinconf_to_config_packed(param, arg); - - return 0; - - default: - return -ENOTSUPP; - } - - return -ENOTSUPP; -} - -static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *configs, unsigned num_configs) -{ - struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param; - u16 arg; - unsigned i, gpio = iproc_pin_to_gpio(pin); - int ret = -ENOTSUPP; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - ret = iproc_gpio_set_pull(chip, gpio, true, false); - if (ret < 0) - goto out; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - ret = iproc_gpio_set_pull(chip, gpio, false, true); - if (ret < 0) - goto out; - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - ret = iproc_gpio_set_pull(chip, gpio, false, false); - if (ret < 0) - goto out; - break; - - case PIN_CONFIG_DRIVE_STRENGTH: - ret = iproc_gpio_set_strength(chip, gpio, arg); - if (ret < 0) - goto out; - break; - - default: - dev_err(chip->dev, "invalid configuration\n"); - return -ENOTSUPP; - } - } /* for each config */ - -out: - return ret; -} - -static const struct pinconf_ops iproc_pconf_ops = { - .is_generic = true, - .pin_config_get = iproc_pin_config_get, - .pin_config_set = iproc_pin_config_set, -}; - -/* - * Iproc GPIO controller supports some PINCONF related configurations such as - * pull up, pull down, and drive strength, when the pin is configured to GPIO - * - * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the - * local GPIO pins - */ -static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) -{ - struct pinctrl_desc *pctldesc = &chip->pctldesc; - struct pinctrl_pin_desc *pins; - struct gpio_chip *gc = &chip->gc; - int i; - - pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); - if (!pins) - return -ENOMEM; - - for (i = 0; i < gc->ngpio; i++) { - pins[i].number = i; - pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, - "gpio-%d", i); - if (!pins[i].name) - return -ENOMEM; - } - - pctldesc->name = dev_name(chip->dev); - pctldesc->pctlops = &iproc_pctrl_ops; - pctldesc->pins = pins; - pctldesc->npins = gc->ngpio; - pctldesc->confops = &iproc_pconf_ops; - - chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); - if (IS_ERR(chip->pctl)) { - dev_err(chip->dev, "unable to register pinctrl device\n"); - return PTR_ERR(chip->pctl); - } - - return 0; -} - -static void iproc_gpio_unregister_pinconf(struct cygnus_gpio *chip) -{ - pinctrl_unregister(chip->pctl); -} - -static const struct of_device_id iproc_gpio_of_match[] = { - { .compatible = "brcm,cygnus-ccm-gpio" }, - { .compatible = "brcm,cygnus-asiu-gpio" }, - { .compatible = "brcm,cygnus-crmu-gpio" }, - { .compatible = "brcm,iproc-gpio" }, - { } -}; - -static int iproc_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct resource *res; - struct iproc_gpio *chip; - struct gpio_chip *gc; - u32 ngpios; - int irq, ret; - - chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); - if (!chip) - return -ENOMEM; - - chip->dev = dev; - platform_set_drvdata(pdev, chip); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - chip->base = devm_ioremap_resource(dev, res); - if (IS_ERR(chip->base)) { - dev_err(dev, "unable to map I/O memory\n"); - return PTR_ERR(chip->base); - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) { - chip->io_ctrl = devm_ioremap_resource(dev, res); - if (IS_ERR(chip->io_ctrl)) { - dev_err(dev, "unable to map I/O memory\n"); - return PTR_ERR(chip->io_ctrl); - } - } - - if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { - dev_err(&pdev->dev, "missing ngpios DT property\n"); - r