From 23bea1be4eea435af42d9971aef8205b71cf7cd3 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Mon, 24 Aug 2020 00:00:25 +0200 Subject: phy: qcom-ipq4019-usb: Constify static phy_ops structs Their only usages is to assign the address to the data field in the of_device_id struct, which is a const void pointer. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn Link: https://lore.kernel.org/r/20200823220025.17588-9-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c index b8ef331e1545..fc7f9df80a7b 100644 --- a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c @@ -48,7 +48,7 @@ static int ipq4019_ss_phy_power_on(struct phy *_phy) return 0; } -static struct phy_ops ipq4019_usb_ss_phy_ops = { +static const struct phy_ops ipq4019_usb_ss_phy_ops = { .power_on = ipq4019_ss_phy_power_on, .power_off = ipq4019_ss_phy_power_off, }; @@ -80,7 +80,7 @@ static int ipq4019_hs_phy_power_on(struct phy *_phy) return 0; } -static struct phy_ops ipq4019_usb_hs_phy_ops = { +static const struct phy_ops ipq4019_usb_hs_phy_ops = { .power_on = ipq4019_hs_phy_power_on, .power_off = ipq4019_hs_phy_power_off, }; -- cgit v1.2.3 From 38af68cb04cf776196099bb0dd079bbcfe57b771 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 25 Aug 2020 10:03:05 +0800 Subject: phy: phy-qcom-apq8064-sata: convert to readl_relaxed_poll_timeout() Use readl_relaxed_poll_timeout() to simplify code, rename local function read_poll_timeout() as poll_timeout() to avoid repeated definition Signed-off-by: Chunfeng Yun Link: https://lore.kernel.org/r/1598320987-25518-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c b/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c index febe0aef68d4..ce91ae7f8dbd 100644 --- a/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c +++ b/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -72,18 +73,12 @@ struct qcom_apq8064_sata_phy { }; /* Helper function to do poll and timeout */ -static int read_poll_timeout(void __iomem *addr, u32 mask) +static int poll_timeout(void __iomem *addr, u32 mask) { - unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); + u32 val; - do { - if (readl_relaxed(addr) & mask) - return 0; - - usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); - } while (!time_after(jiffies, timeout)); - - return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT; + return readl_relaxed_poll_timeout(addr, val, (val & mask), + DELAY_INTERVAL_US, TIMEOUT_MS * 1000); } static int qcom_apq8064_sata_phy_init(struct phy *generic_phy) @@ -137,21 +132,21 @@ static int qcom_apq8064_sata_phy_init(struct phy *generic_phy) writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2); /* PLL Lock wait */ - ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK); + ret = poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK); if (ret) { dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n"); return ret; } /* TX Calibration */ - ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL); + ret = poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL); if (ret) { dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n"); return ret; } /* RX Calibration */ - ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL); + ret = poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL); if (ret) { dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n"); return ret; -- cgit v1.2.3 From dadcf9959ccef45e2958da42850757b4f0ac3751 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Sep 2020 16:11:54 -0700 Subject: phy: qcom-qmp: Move phy mode into struct qmp_phy The phy mode pertains to the phy itself, i.e. 'struct qmp_phy', not the wrapper, i.e. 'struct qcom_qmp'. Move the phy mode into the phy structure to more accurately reflect what is going on. This also cleans up 'struct qcom_qmp' so that it can eventually be the place where qmp wrapper wide data is located, paving the way for the USB3+DP combo phy. Signed-off-by: Stephen Boyd Reviewed-by: Bjorn Andersson Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Link: https://lore.kernel.org/r/20200916231202.3637932-3-swboyd@chromium.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 6e6f992a9524..3fa8338b9503 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1811,6 +1811,7 @@ struct qmp_phy_cfg { * @index: lane index * @qmp: QMP phy to which this lane belongs * @lane_rst: lane's reset controller + * @mode: current PHY mode */ struct qmp_phy { struct phy *phy; @@ -1824,6 +1825,7 @@ struct qmp_phy { unsigned int index; struct qcom_qmp *qmp; struct reset_control *lane_rst; + enum phy_mode mode; }; /** @@ -1842,7 +1844,6 @@ struct qmp_phy { * @phy_mutex: mutex lock for PHY common block initialization * @init_count: phy common block initialization count * @phy_initialized: indicate if PHY has been initialized - * @mode: current PHY mode * @ufs_reset: optional UFS PHY reset handle */ struct qcom_qmp { @@ -1860,7 +1861,6 @@ struct qcom_qmp { struct mutex phy_mutex; int init_count; bool phy_initialized; - enum phy_mode mode; struct reset_control *ufs_reset; }; @@ -2803,9 +2803,8 @@ static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - qmp->mode = mode; + qphy->mode = mode; return 0; } @@ -2818,8 +2817,8 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) void __iomem *pcs_misc = qphy->pcs_misc; u32 intr_mask; - if (qmp->mode == PHY_MODE_USB_HOST_SS || - qmp->mode == PHY_MODE_USB_DEVICE_SS) + if (qphy->mode == PHY_MODE_USB_HOST_SS || + qphy->mode == PHY_MODE_USB_DEVICE_SS) intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; else intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; @@ -2865,7 +2864,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) struct qmp_phy *qphy = qmp->phys[0]; const struct qmp_phy_cfg *cfg = qmp->cfg; - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); /* Supported only for USB3 PHY */ if (cfg->type != PHY_TYPE_USB3) @@ -2891,7 +2890,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) const struct qmp_phy_cfg *cfg = qmp->cfg; int ret = 0; - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); /* Supported only for USB3 PHY */ if (cfg->type != PHY_TYPE_USB3) -- cgit v1.2.3 From e4bc7de8ae166dff1b926d031266c3866f779766 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Sep 2020 16:11:55 -0700 Subject: phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' We already track if any phy inside the qmp wrapper has been initialized by means of the struct qcom_qmp::init_count member. Let's drop the duplicate 'initialized' member to simplify the code a bit. Signed-off-by: Stephen Boyd Reviewed-by: Bjorn Andersson Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Link: https://lore.kernel.org/r/20200916231202.3637932-4-swboyd@chromium.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 3fa8338b9503..26623ddb0751 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1843,7 +1843,6 @@ struct qmp_phy { * @phys: array of per-lane phy descriptors * @phy_mutex: mutex lock for PHY common block initialization * @init_count: phy common block initialization count - * @phy_initialized: indicate if PHY has been initialized * @ufs_reset: optional UFS PHY reset handle */ struct qcom_qmp { @@ -1860,7 +1859,6 @@ struct qcom_qmp { struct mutex phy_mutex; int init_count; - bool phy_initialized; struct reset_control *ufs_reset; }; @@ -2750,7 +2748,6 @@ static int qcom_qmp_phy_enable(struct phy *phy) dev_err(qmp->dev, "phy initialization timed-out\n"); goto err_pcs_ready; } - qmp->phy_initialized = true; return 0; err_pcs_ready: @@ -2794,8 +2791,6 @@ static int qcom_qmp_phy_disable(struct phy *phy) qcom_qmp_phy_com_exit(qmp); - qmp->phy_initialized = false; - return 0; } @@ -2870,7 +2865,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) if (cfg->type != PHY_TYPE_USB3) return 0; - if (!qmp->phy_initialized) { + if (!qmp->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } @@ -2896,7 +2891,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) if (cfg->type != PHY_TYPE_USB3) return 0; - if (!qmp->phy_initialized) { + if (!qmp->init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } -- cgit v1.2.3 From aa968cb1a67e27de8a6d0f2012cffc53f256404a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Sep 2020 16:11:56 -0700 Subject: phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' The serdes I/O region is where the PLL for the phy is controlled. Sometimes the PLL is shared between multiple phys, for example in the PCIe case where there are three phys inside the same wrapper. Other times the PLL is for a single phy, i.e. some USB3 phys. To complete the trifecta we have the USB3+DP combo phy where the USB3 and DP phys each have their own serdes region because they have their own PLL while they both share a common I/O region pertaining to the USB type-c pinout and cable orientation. Let's move the serdes iomem pointer into 'struct qmp_phy' so that we can correlate PLL control to the phy that uses it. This allows us to support the USB3+DP combo phy in this driver. This isn't a problem for the 3-lane/phy PCIe phy because there is a common init function that is the only place the serdes region is programmed. Furthermore, move the configuration data that contains most of the register programming sequences to the qmp phy struct. This data isn't qmp wrapper specific. It is phy specific data used to tune various settings for things like pre-emphasis, bias, etc. Signed-off-by: Stephen Boyd Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Link: https://lore.kernel.org/r/20200916231202.3637932-5-swboyd@chromium.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 113 ++++++++++++++++++------------------ 1 file changed, 56 insertions(+), 57 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 26623ddb0751..271cdf7aaffa 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1801,6 +1801,8 @@ struct qmp_phy_cfg { * struct qmp_phy - per-lane phy descriptor * * @phy: generic phy + * @cfg: phy specific configuration + * @serdes: iomapped memory space for phy's serdes (i.e. PLL) * @tx: iomapped memory space for lane's tx * @rx: iomapped memory space for lane's rx * @pcs: iomapped memory space for lane's pcs @@ -1815,6 +1817,8 @@ struct qmp_phy_cfg { */ struct qmp_phy { struct phy *phy; + const struct qmp_phy_cfg *cfg; + void __iomem *serdes; void __iomem *tx; void __iomem *rx; void __iomem *pcs; @@ -1832,14 +1836,12 @@ struct qmp_phy { * struct qcom_qmp - structure holding QMP phy block attributes * * @dev: device - * @serdes: iomapped memory space for phy's serdes * @dp_com: iomapped memory space for phy's dp_com control block * * @clks: array of clocks required by phy * @resets: array of resets required by phy * @vregs: regulator supplies bulk data * - * @cfg: phy specific configuration * @phys: array of per-lane phy descriptors * @phy_mutex: mutex lock for PHY common block initialization * @init_count: phy common block initialization count @@ -1847,14 +1849,12 @@ struct qmp_phy { */ struct qcom_qmp { struct device *dev; - void __iomem *serdes; void __iomem *dp_com; struct clk_bulk_data *clks; struct reset_control **resets; struct regulator_bulk_data *vregs; - const struct qmp_phy_cfg *cfg; struct qmp_phy **phys; struct mutex phy_mutex; @@ -2480,8 +2480,8 @@ static void qcom_qmp_phy_configure(void __iomem *base, static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; - void __iomem *serdes = qmp->serdes; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; void __iomem *pcs = qphy->pcs; void __iomem *dp_com = qmp->dp_com; int ret, i; @@ -2512,7 +2512,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ret = reset_control_deassert(qmp->resets[i]); if (ret) { dev_err(qmp->dev, "%s reset deassert failed\n", - qmp->cfg->reset_list[i]); + qphy->cfg->reset_list[i]); goto err_rst; } } @@ -2594,10 +2594,11 @@ err_reg_enable: return ret; } -static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp) +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) { - const struct qmp_phy_cfg *cfg = qmp->cfg; - void __iomem *serdes = qmp->serdes; + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; int i = cfg->num_resets; mutex_lock(&qmp->phy_mutex); @@ -2632,7 +2633,7 @@ static int qcom_qmp_phy_enable(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *tx = qphy->tx; void __iomem *rx = qphy->rx; void __iomem *pcs = qphy->pcs; @@ -2757,7 +2758,7 @@ err_clk_enable: if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); err_lane_rst: - qcom_qmp_phy_com_exit(qmp); + qcom_qmp_phy_com_exit(qphy); return ret; } @@ -2765,8 +2766,7 @@ err_lane_rst: static int qcom_qmp_phy_disable(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; clk_disable_unprepare(qphy->pipe_clk); @@ -2789,7 +2789,7 @@ static int qcom_qmp_phy_disable(struct phy *phy) if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); - qcom_qmp_phy_com_exit(qmp); + qcom_qmp_phy_com_exit(qphy); return 0; } @@ -2806,8 +2806,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy, static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) { - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; void __iomem *pcs_misc = qphy->pcs_misc; u32 intr_mask; @@ -2836,8 +2835,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) { - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; void __iomem *pcs_misc = qphy->pcs_misc; @@ -2857,7 +2855,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); @@ -2882,7 +2880,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_phy_cfg *cfg = qphy->cfg; int ret = 0; dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); @@ -2914,10 +2912,10 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) return 0; } -static int qcom_qmp_phy_vreg_init(struct device *dev) +static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); - int num = qmp->cfg->num_vregs; + int num = cfg->num_vregs; int i; qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); @@ -2925,24 +2923,24 @@ static int qcom_qmp_phy_vreg_init(struct device *dev) return -ENOMEM; for (i = 0; i < num; i++) - qmp->vregs[i].supply = qmp->cfg->vreg_list[i]; + qmp->vregs[i].supply = cfg->vreg_list[i]; return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qcom_qmp_phy_reset_init(struct device *dev) +static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; - qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets, + qmp->resets = devm_kcalloc(dev, cfg->num_resets, sizeof(*qmp->resets), GFP_KERNEL); if (!qmp->resets) return -ENOMEM; - for (i = 0; i < qmp->cfg->num_resets; i++) { + for (i = 0; i < cfg->num_resets; i++) { struct reset_control *rst; - const char *name = qmp->cfg->reset_list[i]; + const char *name = cfg->reset_list[i]; rst = devm_reset_control_get(dev, name); if (IS_ERR(rst)) { @@ -2955,10 +2953,10 @@ static int qcom_qmp_phy_reset_init(struct device *dev) return 0; } -static int qcom_qmp_phy_clk_init(struct device *dev) +static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); - int num = qmp->cfg->num_clks; + int num = cfg->num_clks; int i; qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); @@ -2966,7 +2964,7 @@ static int qcom_qmp_phy_clk_init(struct device *dev) return -ENOMEM; for (i = 0; i < num; i++) - qmp->clks[i].id = qmp->cfg->clk_list[i]; + qmp->clks[i].id = cfg->clk_list[i]; return devm_clk_bulk_get(dev, num, qmp->clks); } @@ -3000,12 +2998,6 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) struct clk_init_data init = { }; int ret; - if ((qmp->cfg->type != PHY_TYPE_USB3) && - (qmp->cfg->type != PHY_TYPE_PCIE)) { - /* not all phys register pipe clocks, so return success */ - return 0; - } - ret = of_property_read_string(np, "clock-output-names", &init.name); if (ret) { dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); @@ -3056,7 +3048,8 @@ static const struct phy_ops qcom_qmp_pcie_ufs_ops = { }; static -int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) +int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; @@ -3069,6 +3062,8 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) if (!qphy) return -ENOMEM; + qphy->cfg = cfg; + qphy->serdes = serdes; /* * Get memory resources for each phy lane: * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. @@ -3093,7 +3088,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) * back to old legacy behavior of assuming they can be reached at an * offset from the first lane. */ - if (qmp->cfg->is_dual_lane_phy) { + if (cfg->is_dual_lane_phy) { qphy->tx2 = of_iomap(np, 3); qphy->rx2 = of_iomap(np, 4); if (!qphy->tx2 || !qphy->rx2) { @@ -3126,8 +3121,8 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) snprintf(prop_name, sizeof(prop_name), "pipe%d", id); qphy->pipe_clk = of_clk_get_by_name(np, prop_name); if (IS_ERR(qphy->pipe_clk)) { - if (qmp->cfg->type == PHY_TYPE_PCIE || - qmp->cfg->type == PHY_TYPE_USB3) { + if (cfg->type == PHY_TYPE_PCIE || + cfg->type == PHY_TYPE_USB3) { ret = PTR_ERR(qphy->pipe_clk); if (ret != -EPROBE_DEFER) dev_err(dev, @@ -3139,7 +3134,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) } /* Get lane reset, if any */ - if (qmp->cfg->has_lane_rst) { + if (cfg->has_lane_rst) { snprintf(prop_name, sizeof(prop_name), "lane%d", id); qphy->lane_rst = of_reset_control_get(np, prop_name); if (IS_ERR(qphy->lane_rst)) { @@ -3148,7 +3143,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) } } - if (qmp->cfg->type == PHY_TYPE_UFS || qmp->cfg->type == PHY_TYPE_PCIE) + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ops = &qcom_qmp_pcie_ufs_ops; generic_phy = devm_phy_create(dev, np, ops); @@ -3246,6 +3241,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) struct device_node *child; struct phy_provider *phy_provider; void __iomem *base; + void __iomem *serdes; + const struct qmp_phy_cfg *cfg; int num, id; int ret; @@ -3257,8 +3254,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) dev_set_drvdata(dev, qmp); /* Get the specific init parameters of QMP phy */ - qmp->cfg = of_device_get_match_data(dev); - if (!qmp->cfg) + cfg = of_device_get_match_data(dev); + if (!cfg) return -EINVAL; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -3267,10 +3264,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) return PTR_ERR(base); /* per PHY serdes; usually located at base address */ - qmp->serdes = base; + serdes = base; /* per PHY dp_com; if PHY has dp_com control block */ - if (qmp->cfg->has_phy_dp_com_ctrl) { + if (cfg->has_phy_dp_com_ctrl) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp_com"); base = devm_ioremap_resource(dev, res); @@ -3282,15 +3279,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) mutex_init(&qmp->phy_mutex); - ret = qcom_qmp_phy_clk_init(dev); + ret = qcom_qmp_phy_clk_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_reset_init(dev); + ret = qcom_qmp_phy_reset_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_vreg_init(dev); + ret = qcom_qmp_phy_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to get regulator supplies: %d\n", @@ -3300,7 +3297,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ - if (num > qmp->cfg->nlanes) + if (num > cfg->nlanes) return -EINVAL; qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); @@ -3318,7 +3315,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ - ret = qcom_qmp_phy_create(dev, child, id); + ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -3329,11 +3326,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) * Register the pipe clock provided by phy. * See function description to see details of this pipe clock. */ - ret = phy_pipe_clk_register(qmp, child); - if (ret) { - dev_err(qmp->dev, - "failed to register pipe clock source\n"); - goto err_node_put; + if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { + ret = phy_pipe_clk_register(qmp, child); + if (ret) { + dev_err(qmp->dev, + "failed to register pipe clock source\n"); + goto err_node_put; + } } id++; } -- cgit v1.2.3 From dab7b10ddc83e5cdaef103cc08a162a2a2b03c15 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Sep 2020 16:11:57 -0700 Subject: phy: qcom-qmp: Get dp_com I/O resource by index The dp_com resource is always at index 1 according to the dts files in the kernel. Get this resource by index so that we don't need to make future additions to the DT binding use 'reg-names'. Signed-off-by: Stephen Boyd Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Link: https://lore.kernel.org/r/20200916231202.3637932-6-swboyd@chromium.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 271cdf7aaffa..0dbe9969db37 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3268,13 +3268,9 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) /* per PHY dp_com; if PHY has dp_com control block */ if (cfg->has_phy_dp_com_ctrl) { - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "dp_com"); - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - qmp->dp_com = base; + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->dp_com)) + return PTR_ERR(qmp->dp_com); } mutex_init(&qmp->phy_mutex); -- cgit v1.2.3 From f385b73192c584d0efbfa8903eac3eea7db43744 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Sep 2020 16:11:58 -0700 Subject: phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify We can use the wrapper API here to save some lines and remove the need for the 'base' and 'res' local variable. Suggested-by: Bjorn Andersson Signed-off-by: Stephen Boyd Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Link: https://lore.kernel.org/r/20200916231202.3637932-7-swboyd@chromium.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 0dbe9969db37..1d3fe88aca2e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3237,10 +3237,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; struct device *dev = &pdev->dev; - struct resource *res; struct device_node *child; struct phy_provider *phy_provider; - void __iomem *base; void __iomem *serdes; const struct qmp_phy_cfg *cfg; int num, id; @@ -3258,13 +3256,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) if (!cfg) return -EINVAL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - /* per PHY serdes; usually located at base address */ - serdes = base; + serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(serdes)) + return PTR_ERR(serdes); /* per PHY dp_com; if PHY has dp_com control block */ if (cfg->has_phy_dp_com_ctrl) { -- cgit v1.2.3 From 52e013d0bffa2238746b246074272817ec8e0807 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Sep 2020 16:11:59 -0700 Subject: phy: qcom-qmp: Add support for DP in USB3+DP combo phy Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Stephen Boyd Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 785 +++++++++++++++++++++++++++++++----- drivers/phy/qualcomm/phy-qcom-qmp.h | 80 ++++ 2 files changed, 775 insertions(+), 90 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 1d3fe88aca2e..dbd6422a3233 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1761,6 +1761,16 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *pcs_misc_tbl; int pcs_misc_tbl_num; + /* Init sequence for DP PHY block link rates */ + const struct qmp_phy_init_tbl *serdes_tbl_rbr; + int serdes_tbl_rbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr; + int serdes_tbl_hbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr2; + int serdes_tbl_hbr2_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr3; + int serdes_tbl_hbr3_num; + /* clock ids to be requested */ const char * const *clk_list; int num_clks; @@ -1797,6 +1807,11 @@ struct qmp_phy_cfg { bool no_pcs_sw_reset; }; +struct qmp_phy_combo_cfg { + const struct qmp_phy_cfg *usb_cfg; + const struct qmp_phy_cfg *dp_cfg; +}; + /** * struct qmp_phy - per-lane phy descriptor * @@ -1830,6 +1845,15 @@ struct qmp_phy { struct qcom_qmp *qmp; struct reset_control *lane_rst; enum phy_mode mode; + unsigned int dp_aux_cfg; + struct phy_configure_opts_dp dp_opts; + struct qmp_phy_dp_clks *dp_clks; +}; + +struct qmp_phy_dp_clks { + struct qmp_phy *qphy; + struct clk_hw dp_link_hw; + struct clk_hw dp_pixel_hw; }; /** @@ -2477,6 +2501,295 @@ static void qcom_qmp_phy_configure(void __iomem *base, qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); } +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; + int ret; + + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + + if (cfg->type == PHY_TYPE_DP) { + switch (dp_opts->link_rate) { + case 1620: + qcom_qmp_phy_configure(serdes, cfg->regs, + cfg->serdes_tbl_rbr, + cfg->serdes_tbl_rbr_num); + break; + case 2700: + qcom_qmp_phy_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr, + cfg->serdes_tbl_hbr_num); + break; + case 5400: + qcom_qmp_phy_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr2, + cfg->serdes_tbl_hbr2_num); + break; + case 8100: + qcom_qmp_phy_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr3, + cfg->serdes_tbl_hbr3_num); + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + } + + + if (cfg->has_phy_com_ctrl) { + void __iomem *status; + unsigned int mask, val; + + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], + SERDES_START | PCS_START); + + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; + mask = cfg->mask_com_pcs_ready; + + ret = readl_poll_timeout(status, val, (val & mask), 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, + "phy common block init timed-out\n"); + return ret; + } + } + + return 0; +} + +static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy) +{ + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + + /* Turn on BIAS current for PHY/PLL */ + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); + + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | + DP_PHY_PD_CTL_DP_CLAMP_EN, + qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + + writel(QSERDES_V3_COM_BIAS_EN | + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); + + writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0); + writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); + writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); + writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3); + writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4); + writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5); + writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6); + writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7); + writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8); + writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9); + qphy->dp_aux_cfg = 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); +} + +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { + { 0x00, 0x0c, 0x14, 0x19 }, + { 0x00, 0x0b, 0x12, 0xff }, + { 0x00, 0x0b, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { + { 0x08, 0x0f, 0x16, 0x1f }, + { 0x11, 0x1e, 0x1f, 0xff }, + { 0x19, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy) +{ + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + unsigned int v_level = 0, p_level = 0; + u32 bias_en, drvr_en; + u8 voltage_swing_cfg, pre_emphasis_cfg; + int i; + + for (i = 0; i < dp_opts->lanes; i++) { + v_level = max(v_level, dp_opts->voltage[i]); + p_level = max(p_level, dp_opts->pre[i]); + } + + if (dp_opts->lanes == 1) { + bias_en = 0x3e; + drvr_en = 0x13; + } else { + bias_en = 0x3f; + drvr_en = 0x10; + } + + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; + + /* TODO: Move check to config check */ + if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) + return; + + /* Enable MUX to use Cursor values from these registers */ + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; + + writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); +} + +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + const struct phy_configure_opts_dp *dp_opts = &opts->dp; + struct qmp_phy *qphy = phy_get_drvdata(phy); + + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); + if (qphy->dp_opts.set_voltages) { + qcom_qmp_phy_configure_dp_tx(qphy); + qphy->dp_opts.set_voltages = 0; + } + + return 0; +} + +static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) +{ + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 val, phy_vco_div, status; + unsigned long pixel_freq; + + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; + + /* + * TODO: Assume orientation is CC1 for now and two lanes, need to + * use type-c connector to understand orientation and lanes. + * + * Otherwise val changes to be like below if this code understood + * the orientation of the type-c cable. + * + * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) + * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; + * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) + * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; + * if (orientation == ORIENTATION_CC2) + * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); + */ + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; + writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + + writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); + + switch (dp_opts->link_rate) { + case 1620: + phy_vco_div = 0x1; + pixel_freq = 1620000000UL / 2; + break; + case 2700: + phy_vco_div = 0x1; + pixel_freq = 2700000000UL / 2; + break; + case 5400: + phy_vco_div = 0x2; + pixel_freq = 5400000000UL / 4; + break; + case 8100: + phy_vco_div = 0x0; + pixel_freq = 8100000000UL / 6; + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); + + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); + + writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); + writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + + writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); + + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + udelay(2000); + writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000); +} + +/* + * We need to calibrate the aux setting here as many times + * as the caller tries + */ +static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; + u8 val; + + qphy->dp_aux_cfg++; + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); + val = cfg1_settings[qphy->dp_aux_cfg]; + + writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); + + return 0; +} + static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; @@ -2531,6 +2844,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + /* Default type-c orientation, i.e CC1 */ + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); + qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); @@ -2538,6 +2854,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); + + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); } if (cfg->has_phy_com_ctrl) { @@ -2553,36 +2872,10 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) cfg->pwrdn_ctrl); } - /* Serdes configuration */ - qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl, - cfg->serdes_tbl_num); - - if (cfg->has_phy_com_ctrl) { - void __iomem *status; - unsigned int mask, val; - - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; - mask = cfg->mask_com_pcs_ready; - - ret = readl_poll_timeout(status, val, (val & mask), 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, - "phy common block init timed-out\n"); - goto err_com_init; - } - } - mutex_unlock(&qmp->phy_mutex); return 0; -err_com_init: - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); err_rst: while (++i < cfg->num_resets) reset_control_assert(qmp->resets[i]); @@ -2629,20 +2922,12 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_enable(struct phy *phy) +static int qcom_qmp_phy_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *tx = qphy->tx; - void __iomem *rx = qphy->rx; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - void __iomem *dp_com = qmp->dp_com; - void __iomem *status; - unsigned int mask, val, ready; int ret; - dev_vdbg(qmp->dev, "Initializing QMP phy\n"); if (cfg->no_pcs_sw_reset) { @@ -2669,13 +2954,34 @@ static int qcom_qmp_phy_enable(struct phy *phy) ret = reset_control_assert(qmp->ufs_reset); if (ret) - goto err_lane_rst; + return ret; } ret = qcom_qmp_phy_com_init(qphy); if (ret) return ret; + if (cfg->type == PHY_TYPE_DP) + qcom_qmp_phy_dp_aux_init(qphy); + + return 0; +} + +static int qcom_qmp_phy_power_on(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + void __iomem *pcs = qphy->pcs; + void __iomem *pcs_misc = qphy->pcs_misc; + void __iomem *status; + unsigned int mask, val, ready; + int ret; + + qcom_qmp_phy_serdes_init(qphy); + if (cfg->has_lane_rst) { ret = reset_control_deassert(qphy->lane_rst); if (ret) { @@ -2699,13 +3005,23 @@ static int qcom_qmp_phy_enable(struct phy *phy) qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); + /* Configure special DP tx tunings */ + if (cfg->type == PHY_TYPE_DP) + qcom_qmp_phy_configure_dp_tx(qphy); + qcom_qmp_phy_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); + if (cfg->is_dual_lane_phy) qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); - qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + /* Configure link rate, swing, etc. */ + if (cfg->type == PHY_TYPE_DP) + qcom_qmp_phy_configure_dp_phy(qphy); + else + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + ret = reset_control_deassert(qmp->ufs_reset); if (ret) goto err_lane_rst; @@ -2723,69 +3039,77 @@ static int qcom_qmp_phy_enable(struct phy *phy) if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - - if (cfg->has_phy_dp_com_ctrl) - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); - - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - - if (cfg->type == PHY_TYPE_UFS) { - status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; - mask = PCS_READY; - ready = PCS_READY; - } else { - status = pcs + cfg->regs[QPHY_PCS_STATUS]; - mask = PHYSTATUS; - ready = 0; - } + if (cfg->type != PHY_TYPE_DP) { + /* Pull PHY out of reset state */ + if (!cfg->no_pcs_sw_reset) + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + + if (cfg->type == PHY_TYPE_UFS) { + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; + mask = PCS_READY; + ready = PCS_READY; + } else { + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = PHYSTATUS; + ready = 0; + } - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, "phy initialization timed-out\n"); - goto err_pcs_ready; + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_pcs_ready; + } } return 0; err_pcs_ready: - reset_control_assert(qmp->ufs_reset); clk_disable_unprepare(qphy->pipe_clk); err_clk_enable: if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); err_lane_rst: - qcom_qmp_phy_com_exit(qphy); - return ret; } -static int qcom_qmp_phy_disable(struct phy *phy) +static int qcom_qmp_phy_power_off(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; clk_disable_unprepare(qphy->pipe_clk); - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + if (cfg->type == PHY_TYPE_DP) { + /* Assert DP PHY power down */ + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + } else { + /* PHY reset */ + if (!cfg->no_pcs_sw_reset) + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* stop SerDes and Phy-Coding-Sublayer */ - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - /* Put PHY into POWER DOWN state: active low */ - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - } else { - qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + } } + return 0; +} + +static int qcom_qmp_phy_exit(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); @@ -2794,6 +3118,31 @@ static int qcom_qmp_phy_disable(struct phy *phy) return 0; } +static int qcom_qmp_phy_enable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_init(phy); + if (ret) + return ret; + + ret = qcom_qmp_phy_power_on(phy); + if (ret) + qcom_qmp_phy_exit(phy); + + return ret; +} + +static int qcom_qmp_phy_disable(struct phy *phy) +{ + int ret; + + ret = qcom_qmp_phy_power_off(phy); + if (ret) + return ret; + return qcom_qmp_phy_exit(phy); +} + static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { @@ -2859,7 +3208,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); - /* Supported only for USB3 PHY */ + /* Supported only for USB3 PHY and luckily USB3 is the first phy */ if (cfg->type != PHY_TYPE_USB3) return 0; @@ -2885,7 +3234,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); - /* Supported only for USB3 PHY */ + /* Supported only for USB3 PHY and luckily USB3 is the first phy */ if (cfg->type != PHY_TYPE_USB3) return 0; @@ -2969,7 +3318,7 @@ static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *c return devm_clk_bulk_get(dev, num, qmp->clks); } -static void phy_pipe_clk_release_provider(void *res) +static void phy_clk_release_provider(void *res) { of_clk_del_provider(res); } @@ -3026,9 +3375,202 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) * Roll a devm action because the clock provider is the child node, but * the child node is not actually a device. */ - ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np); + ret = devm_add_action(qmp->dev, phy_clk_release_provider, np); if (ret) - phy_pipe_clk_release_provider(np); + phy_clk_release_provider(np); + + return ret; +} + +/* + * Display Port PLL driver block diagram for branch clocks + * + * +------------------------------+ + * | DP_VCO_CLK | + * | | + * | +-------------------+ | + * | | (DP PLL/VCO) | | + * | +---------+---------+ | + * | v | + * | +----------+-----------+ | + * | | hsclk_divsel_clk_src | | + * | +----------+-----------+ | + * +------------------------------+ + * | + * +---------<---------v------------>----------+ + * | | + * +--------v----------------+ | + * | dp_phy_pll_link_clk | | + * | link_clk | | + * +--------+----------------+ | + * | | + * | | + * v v + * Input to DISPCC block | + * for link clk, crypto clk | + * and interface clock | + * | + * | + * +--------<------------+-----------------+---<---+ + * | | | + * +----v---------+ +--------v-----+ +--------v------+ + * | vco_divided | | vco_divided | | vco_divided | + * | _clk_src | | _clk_src | | _clk_src | + * | | | | | | + * |divsel_six | | divsel_two | | divsel_four | + * +-------+------+ +-----+--------+ +--------+------+ + * | | | + * v---->----------v-------------<------v + * | + * +----------+-----------------+ + * | dp_phy_pll_vco_div_clk | + * +---------+------------------+ + * | + * v + * Input to DISPCC block + * for DP pixel clock + * + */ +static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + switch (req->rate) { + case 1620000000UL / 2: + case 2700000000UL / 2: + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ + return 0; + default: + return -EINVAL; + } +} + +static unsigned long +qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + const struct qmp_phy_dp_clks *dp_clks; + const struct qmp_phy *qphy; + const struct phy_configure_opts_dp *dp_opts; + + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); + qphy = dp_clks->qphy; + dp_opts = &qphy->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + return 1620000000UL / 2; + case 2700: + return 2700000000UL / 2; + case 5400: + return 5400000000UL / 4; + case 8100: + return 8100000000UL / 6; + default: + return 0; + } +} + +static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { + .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, + .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, +}; + +static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + switch (req->rate) { + case 162000000: + case 270000000: + case 540000000: + case 810000000: + return 0; + default: + return -EINVAL; + } +} + +static unsigned long +qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + const struct qmp_phy_dp_clks *dp_clks; + const struct qmp_phy *qphy; + const struct phy_configure_opts_dp *dp_opts; + + dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); + qphy = dp_clks->qphy; + dp_opts = &qphy->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 5400: + case 8100: + return dp_opts->link_rate * 100000; + default: + return 0; + } +} + +static const struct clk_ops qcom_qmp_dp_link_clk_ops = { + .determine_rate = qcom_qmp_dp_link_clk_determine_rate, + .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, +}; + +static struct clk_hw * +qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) +{ + struct qmp_phy_dp_clks *dp_clks = data; + unsigned int idx = clkspec->args[0]; + + if (idx >= 2) { + pr_err("%s: invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + if (idx == 0) + return &dp_clks->dp_link_hw; + + return &dp_clks->dp_pixel_hw; +} + +static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, + struct device_node *np) +{ + struct clk_init_data init = { }; + struct qmp_phy_dp_clks *dp_clks; + int ret; + + dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); + if (!dp_clks) + return -ENOMEM; + + dp_clks->qphy = qphy; + qphy->dp_clks = dp_clks; + + init.ops = &qcom_qmp_dp_link_clk_ops; + init.name = "qmp_dp_phy_pll_link_clk"; + dp_clks->dp_link_hw.init = &init; + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); + if (ret) + return ret; + + init.ops = &qcom_qmp_dp_pixel_clk_ops; + init.name = "qmp_dp_phy_pll_vco_div_clk"; + dp_clks->dp_pixel_hw.init = &init; + ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + ret = devm_add_action(qmp->dev, phy_clk_release_provider, np); + if (ret) + phy_clk_release_provider(np); return ret; } @@ -3040,6 +3582,17 @@ static const struct phy_ops qcom_qmp_phy_gen_ops = { .owner = THIS_MODULE, }; +static const struct phy_ops qcom_qmp_phy_dp_ops = { + .init = qcom_qmp_phy_init, + .configure = qcom_qmp_dp_phy_configure, + .power_on = qcom_qmp_phy_power_on, + .calibrate = qcom_qmp_dp_phy_calibrate, + .power_off = qcom_qmp_phy_power_off, + .exit = qcom_qmp_phy_exit, + .set_mode = qcom_qmp_phy_set_mode, + .owner = THIS_MODULE, +}; + static const struct phy_ops qcom_qmp_pcie_ufs_ops = { .power_on = qcom_qmp_phy_enable, .power_off = qcom_qmp_phy_disable, @@ -3054,7 +3607,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - const struct phy_ops *ops = &qcom_qmp_phy_gen_ops; + const struct phy_ops *ops; char prop_name[MAX_PROP_NAME]; int ret; @@ -3145,6 +3698,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ops = &qcom_qmp_pcie_ufs_ops; + else if (cfg->type == PHY_TYPE_DP) + ops = &qcom_qmp_phy_dp_ops; + else + ops = &qcom_qmp_phy_gen_ops; generic_phy = devm_phy_create(dev, np, ops); if (IS_ERR(generic_phy)) { @@ -3228,6 +3785,10 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }; MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); +static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { + { } +}; + static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, qcom_qmp_phy_runtime_resume, NULL) @@ -3240,8 +3801,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) struct device_node *child; struct phy_provider *phy_provider; void __iomem *serdes; + void __iomem *usb_serdes; + void __iomem *dp_serdes; + const struct qmp_phy_combo_cfg *combo_cfg = NULL; const struct qmp_phy_cfg *cfg; - int num, id; + const struct qmp_phy_cfg *usb_cfg; + const struct qmp_phy_cfg *dp_cfg; + int num, id, expected_phys; int ret; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -3253,21 +3819,45 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) /* Get the specific init parameters of QMP phy */ cfg = of_device_get_match_data(dev); - if (!cfg) - return -EINVAL; + if (!cfg) { + const struct of_device_id *match; + + match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); + if (!match) + return -EINVAL; + + combo_cfg = match->data; + if (!combo_cfg) + return -EINVAL; + + usb_cfg = combo_cfg->usb_cfg; + cfg = usb_cfg; /* Setup clks and regulators */ + } /* per PHY serdes; usually located at base address */ - serdes = devm_platform_ioremap_resource(pdev, 0); + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(serdes)) return PTR_ERR(serdes); /* per PHY dp_com; if PHY has dp_com control block */ - if (cfg->has_phy_dp_com_ctrl) { + if (combo_cfg || cfg->has_phy_dp_com_ctrl) { qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(qmp->dp_com)) return PTR_ERR(qmp->dp_com); } + if (combo_cfg) { + /* Only two serdes for combo PHY */ + dp_serdes = devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(dp_serdes)) + return PTR_ERR(dp_serdes); + + dp_cfg = combo_cfg->dp_cfg; + expected_phys = 2; + } else { + expected_phys = cfg->nlanes; + } + mutex_init(&qmp->phy_mutex); ret = qcom_qmp_phy_clk_init(dev, cfg); @@ -3288,14 +3878,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ - if (num > cfg->nlanes) + if (num > expected_phys) return -EINVAL; qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); if (!qmp->phys) return -ENOMEM; - id = 0; pm_runtime_set_active(dev); pm_runtime_enable(dev); /* @@ -3304,7 +3893,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) */ pm_runtime_forbid(dev); + id = 0; for_each_available_child_of_node(dev->of_node, child) { + if (of_node_name_eq(child, "dp-phy")) { + cfg = dp_cfg; + serdes = dp_serdes; + } else if (of_node_name_eq(child, "usb3-phy")) { + cfg = usb_cfg; + serdes = usb_serdes; + } + /* Create per-lane phy */ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); if (ret) { @@ -3324,6 +3922,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) "failed to register pipe clock source\n"); goto err_node_put; } + } else if (cfg->type == PHY_TYPE_DP) { + ret = phy_dp_clks_register(qmp, qmp->phys[id], child); + if (ret) { + dev_err(qmp->dev, + "failed to register DP clock source\n"); + goto err_node_put; + } } id++; } diff --git a/drivers/phy/qualcomm/phy-q