From 9b5330edf1f8e24a8ca25412e6d341e0fae0ad0a Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Sat, 13 Sep 2014 05:00:46 +0800 Subject: net:fec: add enet refrence clock for i.MX 6SX chip i.MX6sx enet has below clocks for user config: clk_ipg: ipg_clk_s, ipg_clk_mac0_s, 66Mhz clk_ahb: enet system clock, it is enet AXI clock for imx6sx. For imx6sx, it alos is the clock source of interrupt coalescing. The clock range: 200Mhz ~ 266Mhz. clk_ref: refrence clock for tx and rx. For imx6sx enet RGMII mode, the refrence clock is 125Mhz coming from internal PLL or external. In i.MX6sx-arm2 board, the clock is from internal PLL. clk_ref is optional, depends on board. clk_enet_out: The clock can be output from internal PLL. It can supply 50Mhz clock for phy. clk_enet_out is optional, depends on chip and board. clk_ptp: 1588 ts clock. It is optional, depends on chip. The patch add clk_ref to distiguish the different clocks. Signed-off-by: Fugang Duan Signed-off-by: Frank Li Signed-off-by: David S. Miller --- drivers/net/ethernet/freescale/fec.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/net/ethernet/freescale/fec.h') diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index ee41d98b44b6..635772bbfb73 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -272,6 +272,7 @@ struct fec_enet_private { struct clk *clk_ipg; struct clk *clk_ahb; + struct clk *clk_ref; struct clk *clk_enet_out; struct clk *clk_ptp; -- cgit v1.2.3