From f0c8234cb9230e3fc128ab4739f65e30bb00ceb5 Mon Sep 17 00:00:00 2001 From: Takeshi Saito Date: Fri, 8 Feb 2019 20:30:02 +0100 Subject: mmc: renesas_sdhi: Change HW adjustment register according to speed mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF according to the mode. If it is inappropriate, CRC error tends to occur. This adds variable "tap_hs400" for HS400 mode and configures SCC_DT2FF as needed. Signed-off-by: Takeshi Saito [wsa: rebased to upstream and updated commit message] Signed-off-by: Wolfram Sang Reviewed-by: Niklas Söderlund Tested-by: Marek Vasut Signed-off-by: Ulf Hansson --- drivers/mmc/host/renesas_sdhi.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mmc/host/renesas_sdhi.h') diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h index da1e49c45bec..8394a7bb1fc1 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -15,6 +15,7 @@ struct renesas_sdhi_scc { unsigned long clk_rate; /* clock rate for SDR104 */ u32 tap; /* sampling clock position for SDR104 */ + u32 tap_hs400; /* sampling clock position for HS400 */ }; struct renesas_sdhi_of_data { @@ -49,6 +50,7 @@ struct renesas_sdhi { struct pinctrl_state *pins_default, *pins_uhs; void __iomem *scc_ctl; u32 scc_tappos; + u32 scc_tappos_hs400; }; #define host_to_priv(host) \ -- cgit v1.2.3