From 4a268e0879c4044523757b6ac94b56fc7955a116 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Mon, 2 May 2011 18:09:18 +0530 Subject: mmc: msm_sdcc: Use MCI_INT_MASK0 for PIO interrupts Not all targets have IRQ1 line routed from the SD controller to the processor. So we cannot rely on IRQ1 for PIO interrupts. This patch moves all PIO interrupts to IRQ0 and enables the PIO mode. Signed-off-by: Murali Palnati Signed-off-by: Sahitya Tummala Signed-off-by: David Brown Signed-off-by: Chris Ball --- drivers/mmc/host/msm_sdcc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/mmc/host/msm_sdcc.h') diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h index fa626ed915a0..402028d16b86 100644 --- a/drivers/mmc/host/msm_sdcc.h +++ b/drivers/mmc/host/msm_sdcc.h @@ -140,6 +140,11 @@ MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK|MCI_PROGDONEMASK) +#define MCI_IRQ_PIO \ + (MCI_RXDATAAVLBLMASK | MCI_TXDATAAVLBLMASK | MCI_RXFIFOEMPTYMASK | \ + MCI_TXFIFOEMPTYMASK | MCI_RXFIFOFULLMASK | MCI_TXFIFOFULLMASK | \ + MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK | \ + MCI_RXACTIVEMASK | MCI_TXACTIVEMASK) /* * The size of the FIFO in bytes. */ -- cgit v1.2.3