From 3f975d0f71d384825f47c3598d1d5358e40a57f5 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Tue, 15 Sep 2020 16:15:05 +0800 Subject: drm/amdgpu: update athub interrupt harvesting handle GCEA/MMHUB EA error should not result to DF freeze, this is fixed in next generation, but for some reasons the GCEA/MMHUB EA error will result to DF freeze in previous generation, diver should avoid to indicate GCEA/MMHUB EA error as hw fatal error in kernel message by read GCEA/MMHUB err status registers. Changed from V1: make query_ras_error_status function more general make read mmhub er status register more friendly Changed from V2: move ras error status query function into do_recovery workqueue Changed from V3: remove useless code from V2, print GCEA error status instance number Signed-off-by: Stanley.Yang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_offset.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/include') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_offset.h index f41556abfbbc..629a8a3b55e9 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_offset.h @@ -205,6 +205,8 @@ #define mmGCEA_EDC_CNT2_BASE_IDX 0 #define mmGCEA_EDC_CNT3 0x071b #define mmGCEA_EDC_CNT3_BASE_IDX 0 +#define mmGCEA_ERR_STATUS 0x0712 +#define mmGCEA_ERR_STATUS_BASE_IDX 0 // addressBlock: gc_gfxudec // base address: 0x30000 @@ -261,4 +263,4 @@ #define mmRLC_EDC_CNT2 0x4d41 #define mmRLC_EDC_CNT2_BASE_IDX 1 -#endif \ No newline at end of file +#endif -- cgit v1.2.3