From 4898dc4847c2937a5494d70c3f7a59f03d17ccd8 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Thu, 21 May 2020 12:36:30 -0400 Subject: drm/amd/display: Add DCN3 MMHUBHUB Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc_hw_types.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 7bc0be839c9e..a31c75d6d2cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -848,6 +848,42 @@ enum dwb_stereo_type { DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ }; +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + +enum dwb_out_format { + DWB_OUT_FORMAT_32BPP_ARGB = 0, + DWB_OUT_FORMAT_32BPP_RGBA = 1, + DWB_OUT_FORMAT_64BPP_ARGB = 2, + DWB_OUT_FORMAT_64BPP_RGBA = 3 +}; + +enum dwb_out_denorm { + DWB_OUT_DENORM_10BPC = 0, + DWB_OUT_DENORM_8BPC = 1, + DWB_OUT_DENORM_BYPASS = 2 +}; + +enum cm_gamut_remap_select { + CM_GAMUT_REMAP_MODE_BYPASS = 0, + CM_GAMUT_REMAP_MODE_RAMA_COEFF, + CM_GAMUT_REMAP_MODE_RAMB_COEFF, + CM_GAMUT_REMAP_MODE_RESERVED +}; + +enum cm_gamut_coef_format { + CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0, + CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +}; + +struct mcif_warmup_params { + union large_integer start_address; + unsigned int address_increment; + unsigned int region_size; + unsigned int p_vmid; +}; + +#endif + #define MCIF_BUF_COUNT 4 struct mcif_buf_params { -- cgit v1.2.3