From 361b79119a4b7f53f728913b5ed2c8d2d10c16f5 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 30 Aug 2016 17:24:27 +0930 Subject: gpio: Add Aspeed driver The Aspeed SoCs contain GPIOs banked by letter, where each bank contains 8 pins. The GPIO banks are then grouped in sets of four in the register layout. The implementation exposes multiple banks through the one driver and requests and releases pins via the pinctrl subsystem. The hardware supports generation of interrupts from all GPIO-capable pins. A number of hardware features are not yet supported: Configuration of interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance for output ports. Signed-off-by: Joel Stanley Signed-off-by: Alistair Popple Signed-off-by: Jeremy Kerr Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij --- drivers/gpio/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpio/Kconfig') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 5eb7c864d4a5..17842e6a56dc 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -106,6 +106,13 @@ config GPIO_AMDPT driver for GPIO functionality on Promontory IOHub Require ACPI ASL code to enumerate as a platform device. +config GPIO_ASPEED + tristate "Aspeed GPIO support" + depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO + select GPIOLIB_IRQCHIP + help + Say Y here to support Aspeed AST2400 and AST2500 GPIO controllers. + config GPIO_ATH79 tristate "Atheros AR71XX/AR724X/AR913X GPIO support" default y if ATH79 -- cgit v1.2.3